公开(公告)号：US20150131894A1

公开(公告)日：2015-05-14

申请号：US14540021

申请日：2014-11-12

Applicant: Synopsys, Inc.

Inventor： Mahantesh Narwade ,  Namit Gupta ,  Kaushik De ,  Rajarshi Mukherjee ,  Suman Nandan ,  Subhamoy Pal

IPC: G06T7/00 ,  G06K9/48

CPC classification number: G06T7/0008 ,  G06F17/504 ,  G06F17/5081 ,  G06K9/48 ,  G06T2207/30148

Abstract: A method for controlling the functional output of a verification tool upon receipt of a circuit description comprises searching for a predetermined base pattern in the circuit description. The method further comprises searching for predetermined sub-patterns that are assigned to the base pattern, in the circuit description. The method further comprises the validation of each found sub-pattern based on a predetermined rule to minimize the set of reported errors that based on verification of the circuit description.

Abstract translation: 用于在接收到电路描述时控制验证工具的功能输出的方法包括在电路描述中搜索预定的基本模式。 该方法还包括在电路描述中搜索分配给基本模式的预定子模式。 该方法还包括基于预定规则对每个找到的子模式进行验证，以使基于电路描述的验证的报告错误集合最小化。

公开(公告)号：US09529948B2

公开(公告)日：2016-12-27

申请号：US14529048

申请日：2014-10-30

Applicant: Synopsys, Inc.

Inventor： Kaushik De ,  Mahantesh Narwade ,  Rajarshi Mukherjee ,  Namit Gupta

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F2217/78

Abstract: A method for functional verification of a circuit description comprises generating a first set of crossover paths based on the circuit description, generating a low power information based on a power design description associated with the circuit description, the low power information determining a set of power state combinations, and generating a second set of crossover paths based on the first set of crossover paths and the low power information, the second set of crossover paths being a subset of the first set of crossover paths. Each of the second set of crossover paths is evaluated to identify circuit description errors, in particular functional circuit description errors.

Abstract translation: 一种用于电路描述的功能验证的方法包括基于所述电路描述生成第一组交叉路径，基于与所述电路描述相关联的功率设计描述生成低功率信息，所述低功率信息确定一组功率状态 组合，以及基于所述第一组交叉路径和所述低功率信息生成第二组交叉路径，所述第二组交叉路径是所述第一组交叉路径的子集。 评估第二组交叉路径中的每一个以识别电路描述错误，特别是功能电路描述错误。

公开(公告)号：US09886753B2

公开(公告)日：2018-02-06

申请号：US14540021

申请日：2014-11-12

Applicant: Synopsys, Inc.

Inventor： Mahantesh Narwade ,  Namit Gupta ,  Kaushik De ,  Rajarshi Mukherjee ,  Suman Nandan ,  Subhamoy Pal

IPC: G06T7/00 ,  G06F17/50 ,  G06K9/48

CPC classification number: G06T7/0008 ,  G06F17/504 ,  G06F17/5081 ,  G06K9/48 ,  G06T2207/30148

Abstract: A method for controlling the functional output of a verification tool upon receipt of a circuit description comprises searching for a predetermined base pattern in the circuit description. The method further comprises searching for predetermined sub-patterns that are assigned to the base pattern, in the circuit description. The method further comprises the validation of each found sub-pattern based on a predetermined rule to minimize the set of reported errors that based on verification of the circuit description.

公开(公告)号：US20140258954A1

公开(公告)日：2014-09-11

申请号：US13786599

申请日：2013-03-06

Applicant: SYNOPSYS, INC.

Inventor： Kaushik De ,  Kevin M. Harer ,  Rajarshi Mukherjee ,  Mahantesh Narwade

IPC: G06F17/50

CPC classification number: G06F17/504

Abstract: Verification-result ranking techniques for root cause analysis are disclosed using violation report analysis and violation weighting. Violation reports are unwieldy and result from a variety of design and process checks. The check coverage can overlap, causing a specific violation to trigger multiple reported violations. High turn around times for violation report analysis increase the risk that selective violation analysis will inadvertently suppress real design bugs. This reduces the odds that static checker reports alone will meet design sign-off criteria. Determining relationships among a plurality of violations for a design permits clustering violations into hot spots. Identification of primary and subsequent contributors to the plurality of violations is based on the relationships among violations. The hot spot with the highest weight is identified, and then subsequent violations are identified to maximize violation coverage. The result is greater efficiency of design violation identification and resolution.

Abstract translation: 使用违规报告分析和违规加权披露了根本原因分析的验证结果排序技术。 违规报告是笨重的，并且是由各种设计和流程检查产生的。 检查覆盖可能重叠，导致特定违规触发多个报告的违规。 违规报告分析的高转时间增加了选择性违规分析将无意中压制真实设计错误的风险。 这减少了静态检查器报告单独符合设计签字标准的可能性。 确定设计的多个违规之间的关系允许将违规聚类到热点。 确定多个违规行为的主要和后续贡献者是基于违规行为之间的关系。 确定重量最大的热点，然后确定随后的违规行为，以最大限度地发挥违规覆盖率。 结果是设计违规识别和解决方案的效率更高。

公开(公告)号：US09032339B2

公开(公告)日：2015-05-12

申请号：US13786599

申请日：2013-03-06

Applicant: Synopsys, Inc.

Inventor： Kaushik De ,  Kevin M. Harer ,  Rajarshi Mukherjee ,  Mahantesh Narwade

IPC: G06F17/50

CPC classification number: G06F17/504

Abstract: Verification-result ranking techniques for root cause analysis are disclosed using violation report analysis and violation weighting. Violation reports are unwieldy and result from a variety of design and process checks. The check coverage can overlap, causing a specific violation to trigger multiple reported violations. High turn around times for violation report analysis increase the risk that selective violation analysis will inadvertently suppress real design bugs. This reduces the odds that static checker reports alone will meet design sign-off criteria. Determining relationships among a plurality of violations for a design permits clustering violations into hot spots. Identification of primary and subsequent contributors to the plurality of violations is based on the relationships among violations. The hot spot with the highest weight is identified, and then subsequent violations are identified to maximize violation coverage. The result is greater efficiency of design violation identification and resolution.

Abstract translation: 使用违规报告分析和违规加权披露了根本原因分析的验证结果排序技术。 违规报告是笨重的，并且是由各种设计和流程检查产生的。 检查覆盖可能重叠，导致特定违规触发多个报告的违规。 违规报告分析的高转时间增加了选择性违规分析将无意中压制真实设计错误的风险。 这减少了静态检查器报告单独符合设计签字标准的可能性。 确定设计的多个违规之间的关系允许将违规聚类到热点。 确定多个违规行为的主要和后续贡献者是基于违规行为之间的关系。 确定重量最大的热点，然后确定随后的违规行为，以最大限度地发挥违规覆盖率。 结果是设计违规识别和解决方案的效率更高。

公开(公告)号：US20150121326A1

公开(公告)日：2015-04-30

申请号：US14529048

申请日：2014-10-30

Applicant: Synopsys, Inc.

Inventor： Kaushik De ,  Mahantesh Narwade ,  Rajarshi Mukherjee ,  Namit Gupta

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F2217/78

Abstract: A method for functional verification of a circuit description comprises generating a first set of crossover paths based on the circuit description, generating a low power information based on a power design description associated with the circuit description, the low power information determining a set of power state combinations, and generating a second set of crossover paths based on the first set of crossover paths and the low power information, the second set of crossover paths being a subset of the first set of crossover paths. Each of the second set of crossover paths is evaluated to identify circuit description errors, in particular functional circuit description errors.

Abstract translation: 一种用于电路描述的功能验证的方法包括基于所述电路描述生成第一组交叉路径，基于与所述电路描述相关联的功率设计描述生成低功率信息，所述低功率信息确定一组功率状态 组合，以及基于所述第一组交叉路径和所述低功率信息生成第二组交叉路径，所述第二组交叉路径是所述第一组交叉路径的子集。 评估第二组交叉路径中的每一个以识别电路描述错误，特别是功能电路描述错误。