公开(公告)号：US11222154B2

公开(公告)日：2022-01-11

申请号：US17063059

申请日：2020-10-05

Applicant: Synopsys, Inc.

Inventor： Kaushik De ,  Rajarshi Mukherjee ,  David L. Allen ,  Bhaskar Pal ,  Sanjay Gulati ,  Gaurav Pratap ,  Nishant Patel ,  Malitha Kulatunga ,  Sachin Bansal

IPC: G06F30/3308 ,  G06F1/3296 ,  G06F1/28 ,  G06F119/06

Abstract: State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical group to create a merged power state table for the hierarchical group; removing, by a processing device, any power states associated with the non-peripheral supplies from the merged power state table to create a reduced power state table; and modeling a reduced logical block based on the reduced power state table.

公开(公告)号：US20220075920A1

公开(公告)日：2022-03-10

申请号：US17463040

申请日：2021-08-31

Applicant: Synopsys, Inc.

Inventor： Sachin Bansal ,  Bhaskar Pal ,  Kamalesh Ghosh ,  Tushar Parikh ,  Soumik Das Choudhury ,  Hasindu Ramanayake

IPC: G06F30/3323 ,  G06F30/3315

Abstract: A power intent specification specifies the desired power intent for a design of an integrated circuit, for example the states of the power domains under different conditions. Power-aware formal properties describe desired behaviors specified by the power intent specification. Falsified power-aware formal properties indicate that the design does not exhibit the desired behavior. In addition, a debug context database contains debug contexts for static-check violations resulting from power-aware static checking of the design. Static checking checks for compliance with the power intent specification based on a static structure of the design. Falsified power-aware formal properties ae matched against the static-check violations. A data structure is generated, associating debug contexts for the matching static-check violations as possible causes of the falsified power-aware formal properties.