公开(公告)号：US20240146285A1

公开(公告)日：2024-05-02

申请号：US18458821

申请日：2023-08-30

Applicant: VIETTEL GROUP

Inventor： Thai Ha Le ,  Ha My Bui ,  Anh Tuan Khong

IPC: H03K3/037 ,  G01R31/3185

CPC classification number: H03K3/037 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318552

Abstract: Described is a design to synchronize and prevent any clock timing issues associated with two clock domain crossing (CDC) in Design for Testing (DFT) and other CDC applications. In order to avoid any meta-stability issues associated with the sensitive edges of the two clock domains, the synchronization scheme splits the incoming data of the first clock domain into three branches, from which a finite state machine is to choose the correct branch for data transfer to the second clock domain. The selected branch will be the ‘safe’ one that guarantees there will be no timing issue at the second clock domain. This methodology can be applied in IC design that needs to optimize area and performance.

公开(公告)号：US20240143881A1

公开(公告)日：2024-05-02

申请号：US18358449

申请日：2023-07-25

Applicant: VIETTEL GROUP

Inventor： Thai Ha Le ,  Ha My Bui ,  Anh Tuan Khong

IPC: G06F30/333 ,  G06F30/3312

CPC classification number: G06F30/333 ,  G06F30/3312

Abstract: The present invention discloses a DFT (Design for test) methodology to integrate synchronous double-clock latches to synchronize data transferring between two asynchronous clock domains, where the conventional lockup-latches (asynchronous latches) are automatically inserted to connect/combine the two independent asynchronous DFT chains for a more compacted solution. If the asynchronous latches are replaced by the synchronous double-clock ones, the static timing analysis (STA) will check both ends of the latches, therefore, the full combined chain is safe from the setup-hold issues. This method utilizes the automatic flow of asynchronous latches insertion to connect independent DFT chains. Then these conventional latches are replaced by synchronous ones. Both the synthesis, the physical implementation flows in the DFT design and the automatic-test pattern generation (ATPG) scheme have been modified to match these replacements.