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    System and method for reducing power of a circuit using critical signal analysis
    3.
    发明授权
    System and method for reducing power of a circuit using critical signal analysis 有权
    使用关键信号分析降低电路功率的系统和方法

    公开(公告)号：US09405872B2

    公开(公告)日：2016-08-02

    申请号：US14600234

    申请日：2015-01-20

    Applicant: Synopsys, Inc.

    Inventor： Solaiman Rahim ,  Sean Safarpour ,  Shekaripuram V. Venkatesh ,  Siddharth Guha ,  Fahim Rahim

    IPC: G06F17/50

    CPC classification number: G06F17/5031 ,  G06F2217/06 ,  G06F2217/08 ,  G06F2217/78 ,  G06F2217/84

    Abstract: A system and methods provide for an analysis of at least a portion of an integrated circuit (IC) that comprises a plurality of modules, for the purpose of identifying signals that can be indicative of the activity of the modules. By analyzing the activity of these signal immediately before and immediately after each module going from non-idle to idle and from idle to non-idle respectively, it is possible to determine which signals provide an indication that the module should be shut down. If the module can be shut down in idle state, then these input signals may be used as control signals for this purpose. By reporting to a designer the role of such signals a simple design change for detecting the activity and controlling the module, can save on power consumption, in ways not previously detected by the designer.

    Abstract translation: 为了识别可以指示模块的活动的信号，系统和方法提供对包括多个模块的集成电路（IC）的至少一部分的分析。 通过在每个模块从非空闲状态到空闲状态之前和之后立即分析这些信号的活动，分别从空闲到非空闲状态分析这些信号的活动，可以确定哪些信号提供模块应该被关闭的指示。 如果模块可以在空闲状态下关闭，那么这些输入信号可以用作这个目的的控制信号。 通过向设计人员报告这种信号的作用，用于检测活动和控制模块的简单设计更改可以以先前未被设计人员检测到的方式节省功耗。

    Multi-cycle power analysis of integrated circuit designs
    8.
    发明授权
    Multi-cycle power analysis of integrated circuit designs 有权

    公开(公告)号：US12093620B1

    公开(公告)日：2024-09-17

    申请号：US18385285

    申请日：2023-10-30

    Applicant: Synopsys, Inc.

    Inventor： George Guangqiu Chen ,  Solaiman Rahim

    IPC: G06F30/30 ,  G06F30/3315 ,  G06F119/06 ,  G06F119/12

    CPC classification number: G06F30/3315 ,  G06F2119/06 ,  G06F2119/12

    Abstract: A method includes: receiving value changes corresponding to timestamped logic value changes in recorded signals from a verification run of an integrated circuit (IC) design; generating recorded logic vectors from the value changes, each of the recorded logic vectors being associated with a corresponding signal identifier, each of the recorded logic vectors including a recorded logic values over a window of consecutive clock cycles computed from one or more value changes associated with the corresponding signal identifier and having timestamps within the window of consecutive clock cycles; determining, by a processor, inferred logic vectors including inferred logic values corresponding to signals output by cells of the IC design based on propagating the recorded logic values of the recorded logic vectors through the cells; and computing per-cycle power characteristics of the IC design based on the recorded logic vectors and the inferred logic vectors.

    Glitch source identification and ranking
    10.
    发明授权
    Glitch source identification and ranking 有权

    公开(公告)号：US11651131B2

    公开(公告)日：2023-05-16

    申请号：US17335976

    申请日：2021-06-01

    Applicant: Synopsys, Inc.

    Inventor： Vaibhav Jain ,  Solaiman Rahim ,  Myunghoon Yoon ,  Qing Su

    IPC: G06F30/3312 ,  G06F119/06 ,  G06F119/12

    CPC classification number: G06F30/3312 ,  G06F2119/06 ,  G06F2119/12

    Abstract: Glitch source identification and ranking is provided by: identifying a plurality of glitch sources in a circuit layout; back referencing the plurality of glitch sources to corresponding lines in a Resistor Transistor Logic (RTL) file defining the plurality of glitch sources; identifying, in the circuit layout, a plurality of glitch terminuses associated with the plurality of glitch sources; determining a plurality of glitch power consumption values associated with the plurality of glitch sources based on fanouts in the circuit layout extending from the plurality of glitch sources to the plurality of glitch terminuses; ranking, by a processor, the plurality of glitch sources based on corresponding glitch power consumption values of the plurality of glitch power consumption values corresponding to individual glitch sources of the plurality of glitch sources; and reporting the corresponding lines in the RTL file associated with the ranked plurality of glitch sources.

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