公开(公告)号：US11726899B2

公开(公告)日：2023-08-15

申请号：US17454589

申请日：2021-11-11

Applicant: Synopsys, Inc.

Inventor： Gagan Vishal Jain ,  Johnson Adaikalasamy ,  Alexander John Wakefield ,  Ritesh Mittal ,  Solaiman Rahim ,  Olivier Coudert

IPC: G06F11/36 ,  G06F30/331

CPC classification number: G06F11/3652 ,  G06F11/3636 ,  G06F11/3656 ,  G06F30/331

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

公开(公告)号：US10120965B2

公开(公告)日：2018-11-06

申请号：US15278659

申请日：2016-09-28

Applicant: Synopsys, Inc.

Inventor： Johnson Adaikalasamy ,  Gagan Vishal Jain ,  Stanislav Margolin

IPC: G06F9/455 ,  G06F17/50

Abstract: A disclosed system of an emulation environment performs a simulation to construct a waveform of a target signal based on signals traced by an emulator for a time frame including multiple clock cycles. In one embodiment, a simulation is performed in a manner that an input of the logic gate, in a first duration of the time frame at which an output of the logic gate depends on the input, is analyzed to obtain the output, and the input of the logic gate, in a second duration of the time frame at which the output of the logic gate is independent, is omitted. In one aspect, the input of the logic gate is simulated for the first duration based on a periodicity in a waveform of the input in the first duration.

公开(公告)号：US12001317B2

公开(公告)日：2024-06-04

申请号：US18342361

申请日：2023-06-27

Applicant: Synopsys, Inc.

Inventor： Gagan Vishal Jain ,  Johnson Adaikalasamy ,  Alexander John Wakefield ,  Ritesh Mittal ,  Solaiman Rahim ,  Olivier Coudert

IPC: G06F11/36 ,  G06F30/331

CPC classification number: G06F11/3652 ,  G06F11/3636 ,  G06F11/3656 ,  G06F30/331

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

公开(公告)号：US11200149B2

公开(公告)日：2021-12-14

申请号：US15811010

申请日：2017-11-13

Applicant: Synopsys, Inc.

Inventor： Gagan Vishal Jain ,  Johnson Adaikalasamy ,  Alexander John Wakefield ,  Ritesh Mittal ,  Solaiman Rahim ,  Olivier Coudert

IPC: G06F11/36 ,  G06F30/331

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

公开(公告)号：US20230342283A1

公开(公告)日：2023-10-26

申请号：US18342361

申请日：2023-06-27

Applicant: Synopsys, Inc.

Inventor： Gagan Vishal Jain ,  Johnson Adaikalasamy ,  Alexander John Wakefield ,  Ritesh Mittal ,  Solaiman Rahim ,  Olivier Coudert

IPC: G06F11/36 ,  G06F30/331

CPC classification number: G06F11/3652 ,  G06F11/3636 ,  G06F11/3656 ,  G06F30/331

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

公开(公告)号：US20220066909A1

公开(公告)日：2022-03-03

申请号：US17454589

申请日：2021-11-11

Applicant: Synopsys, Inc.

Inventor： Gagan Vishal Jain ,  Johnson Adaikalasamy ,  Alexander John Wakefield ,  Ritesh Mittal ,  Solaiman Rahim ,  Olivier Coudert

IPC: G06F11/36 ,  G06F30/331

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

公开(公告)号：US20180137031A1

公开(公告)日：2018-05-17

申请号：US15811010

申请日：2017-11-13

Applicant: Synopsys, Inc.

Inventor： Gagan Vishal Jain ,  Johnson Adaikalasamy ,  Alexander John Wakefield ,  Ritesh Mittal ,  Solaiman Rahim ,  Olivier Coudert

IPC: G06F11/36 ,  G06F17/50

CPC classification number: G06F11/3652 ,  G06F11/3636 ,  G06F11/3656 ,  G06F17/5027

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

公开(公告)号：US10331825B2

公开(公告)日：2019-06-25

申请号：US16123915

申请日：2018-09-06

Applicant: Synopsys, Inc.

Inventor： Johnson Adaikalasamy ,  Gagan Vishal Jain ,  Stanislav Margolin

IPC: G06F17/50

Abstract: A disclosed system of an emulation environment performs a simulation to construct a waveform of a target signal based on signals traced by an emulator for a time frame including multiple clock cycles. In one embodiment, a simulation is performed in a manner that an input of the logic gate, in a first duration of the time frame at which an output of the logic gate depends on the input, is analyzed to obtain the output, and the input of the logic gate, in a second duration of the time frame at which the output of the logic gate is independent, is omitted. In one aspect, the input of the logic gate is simulated for the first duration based on a periodicity in a waveform of the input in the first duration.

公开(公告)号：US20190005178A1

公开(公告)日：2019-01-03

申请号：US16123915

申请日：2018-09-06

Applicant: Synopsys, Inc.

Inventor： Johnson Adaikalasamy ,  Gagan Vishal Jain ,  Stanislav Margolin

IPC: G06F17/50

CPC classification number: G06F17/5027 ,  G06F17/5031 ,  G06F2217/84

Abstract: A disclosed system of an emulation environment performs a simulation to construct a waveform of a target signal based on signals traced by an emulator for a time frame including multiple clock cycles. In one embodiment, a simulation is performed in a manner that an input of the logic gate, in a first duration of the time frame at which an output of the logic gate depends on the input, is analyzed to obtain the output, and the input of the logic gate, in a second duration of the time frame at which the output of the logic gate is independent, is omitted. In one aspect, the input of the logic gate is simulated for the first duration based on a periodicity in a waveform of the input in the first duration.

公开(公告)号：US20170091360A1

公开(公告)日：2017-03-30

申请号：US15278659

申请日：2016-09-28

Applicant: Synopsys, Inc.

Inventor： Johnson Adaikalasamy ,  Gagan Vishal Jain ,  Stanislav Margolin

IPC: G06F17/50

CPC classification number: G06F17/5027 ,  G06F17/5031 ,  G06F2217/84

Abstract: A disclosed system of an emulation environment performs a simulation to construct a waveform of a target signal based on signals traced by an emulator for a time frame including multiple clock cycles. In one embodiment, a simulation is performed in a manner that an input of the logic gate, in a first duration of the time frame at which an output of the logic gate depends on the input, is analyzed to obtain the output, and the input of the logic gate, in a second duration of the time frame at which the output of the logic gate is independent, is omitted. In one aspect, the input of the logic gate is simulated for the first duration based on a periodicity in a waveform of the input in the first duration.