知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

4 records (took 0.018 seconds)

    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20250036839A1

    公开(公告)日：2025-01-30

    申请号：US18408590

    申请日：2024-01-10

    Applicant: SK hynix Inc.

    Inventor： Jung Hyun KWON ,  Min Seob LEE

    IPC: G06F30/3312 ,  G06F30/3947 ,  G06F119/12

    Abstract: Disclosed is a semiconductor device and a semiconductor system including the same, the semiconductor device includes a plurality of pads, a data pattern analysis circuit configured to generate analysis signals by analyzing a data pattern of each of data mapped to each of the plurality of pads, a data remapping circuit configured to re-determine a relationship between the data and the plurality of pads based on the analysis signals, and remap the data to the plurality of pads based on the re-determined relationship, and an output circuit configured to output the remapped data through the plurality of pads.

    MEMORY CONTROLLER INCLUDING ARBITER, MEMORY SYSTEM AND OPERATION METHOD OF THE MEMORY CONTROLLER
    2.
    发明公开
    MEMORY CONTROLLER INCLUDING ARBITER, MEMORY SYSTEM AND OPERATION METHOD OF THE MEMORY CONTROLLER 审中-公开

    公开(公告)号：US20240126443A1

    公开(公告)日：2024-04-18

    申请号：US18105882

    申请日：2023-02-06

    Applicant: SK hynix Inc.

    Inventor： Jung Hyun KWON ,  Min Seob LEE

    IPC: G06F3/06

    CPC classification number: G06F3/0613 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673

    Abstract: A memory controller includes: a request buffer storing read and write requests of a first rank, and read and write requests of a second rank; an arbiter determining a first request and second requests among the stored requests, the second requests to be issued after the first request according to a descending priority, such that a B request has a higher priority than a C request among the second requests; and a command generator generating commands to be issued to the first rank and the second rank according to the issue order of the first and second requests, wherein the B request is a command whose type and rank are different from those of the first request, and wherein the C request is a command whose type is the same as the type of the first request and whose rank is different from the rank of the first request.

    ALL DIGITAL PHASE LOCKED LOOP
    3.
    发明申请
    ALL DIGITAL PHASE LOCKED LOOP 审中-公开

    公开(公告)号：US20180183447A1

    公开(公告)日：2018-06-28

    申请号：US15795703

    申请日：2017-10-27

    Applicant: SK hynix Inc. ,  POSTECH ACADEMY-INDUSTRY FOUNDATION

    Inventor： Jae Yoon SIM ,  Min Seob LEE ,  In Hwa JUNG ,  Yong Ju KIM

    IPC: H03L7/099 ,  H03L7/07

    CPC classification number: H03L7/0992 ,  H03L7/07

    Abstract: An all digital phase locked loop (ADPLL) includes an integer part phase processing circuit that outputs an integer part frequency signal using a first value and a second value. The first value is obtained by counting edges of one of a plurality of output clock signals. The second value indicates current edge position information on an edge position of an external reference clock signal with respect to the plurality of output clock signals. The ADPLL further includes a fraction part phase processing circuit that selects two adjacent output clock signals of the plurality of output clock signals according to a prediction selection signal and that generates a fraction part frequency signal using the fraction part phase signal, the prediction selection signal being generated according to a fraction part phase signal indicating fraction part phase information and a signal indicating the current edge position information.

Patent Agency Ranking