公开(公告)号：US20200349089A1

公开(公告)日：2020-11-05

申请号：US16712478

申请日：2019-12-12

Applicant: SK hynix Inc.

Inventor： Seung Gyu JEONG ,  Dong Gun KIM

IPC: G06F12/123 ,  G06F12/0804

Abstract: A cache system includes a cache memory having a plurality of blocks, a dirty line list storing status information of a predetermined number of dirty lines among dirty lines in the plurality of blocks, and a cache controller controlling a data caching operation of the cache memory and providing statuses and variation of statuses of the dirty lines, according to the data caching operation, to the dirty line list. The cache controller performs a control operation to always store status information of a least-recently-used (LRU) dirty line into a predetermined storage location of the dirty line list.

公开(公告)号：US20240345749A1

公开(公告)日：2024-10-17

申请号：US18464270

申请日：2023-09-11

Applicant: SK hynix Inc.

Inventor： Jung Hyun KWON ,  Dong Gun KIM ,  Min Seob LEE ,  Kwang Hyo JEONG

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0634 ,  G06F3/0616 ,  G06F3/0625 ,  G06F3/0683 ,  G06F12/0223 ,  G06F2212/1028 ,  G06F2212/1036

Abstract: A memory system includes a memory device comprising plural memory groups, and a controller configured to independently set or adjust a page close time or a page open time for a row or a page in each of the plural memory groups based on whether there is a request to be transferred into each of the plural memory groups.

公开(公告)号：US20220147464A1

公开(公告)日：2022-05-12

申请号：US17585305

申请日：2022-01-26

Applicant: SK hynix Inc.

Inventor： Seung Gyu JEONG ,  Dong Gun KIM

IPC: G06F12/123 ,  G06F12/0804

Abstract: A cache system includes a cache memory having a plurality of blocks, a dirty line list storing status information of a predetermined number of dirty lines among dirty lines in the plurality of blocks, and a cache controller controlling a data caching operation of the cache memory and providing statuses and variation of statuses of the dirty lines, according to the data caching operation, to the dirty line list. The cache controller performs a control operation to always store status information of a least-recently-used (LRU) dirty line into a predetermined storage location of the dirty line list.