Memory bus protection
    2.
    发明授权

    公开(公告)号:US12118132B2

    公开(公告)日:2024-10-15

    申请号:US17266369

    申请日:2019-08-06

    发明人: Scott Best

    摘要: A first address bus may be located in an upper layer of an integrated circuit that is associated with a memory and a memory controller. The first address bus may receive a first portion of a memory address. A second address bus may be located in a lower layer of the integrated circuit where the second address bus is to receive a second portion of the memory address. Furthermore, a data bus may be located in an intermediate layer where the data bus is to receive data corresponding to the memory address from the memory and may transmit the data to the memory controller. The intermediate layer may be between the upper layer and the lower layer. A layout of the signals of the data bus may vertically overlap with a layout of signals of the first address bus and a layout of signals of the second address bus.

    Method, Apparatus and Electronic Device for Controlling Access of USB Device

    公开(公告)号:US20240320380A1

    公开(公告)日:2024-09-26

    申请号:US18678110

    申请日:2024-05-30

    IPC分类号: G06F21/85

    CPC分类号: G06F21/85

    摘要: The disclosure relates to a method for controlling access of a USB device, the method is applied to a USB access control device which is connected with a protected device through interfaces. In this way, the data of the protected device can be protected through the USB access control device which is externally connected to the protected equipment. The data security of the protected device can be ensured without installing security protection software. The USB access control device can determine whether to turn on the switch in the USB access control device according to the descriptor/descriptors of the USB device. If each one of the descriptors of the USB device is the same as that in the registration information of the USB device, the switch in the USB access control device is turn on, so that the USB device can communicate with the protected device.

    System on chip firewall memory architecture

    公开(公告)号:US12101293B2

    公开(公告)日:2024-09-24

    申请号:US17392497

    申请日:2021-08-03

    摘要: In described examples, a system on a chip (SoC) and method for sending messages in the SoC include determining locations of initiator-side firewall block and receiver-side firewall block memories using respective pointers to the firewall block memories stored in a single, contiguous memory. Addresses of the pointers within the single memory depend on respective unique firewall identifiers of the firewall blocks. An exclusive security configuration controller uses the pointers to configure the firewall blocks over a security bus which is electrically isolated from a system bus. The system bus is used to send messages from sending functional blocks to receiving functional blocks. The initiator-side firewall block adds a message identifier to messages. The message identifier depends on the initiator-side firewall block's configuration settings. The receiver-side firewall block controls permission for the receiving functional block to access the message, depending on the message identifier and the receiver-side firewall block's configuration settings.