Queue Versioning
    2.
    发明公开
    Queue Versioning 审中-公开

    公开(公告)号:US20240346071A1

    公开(公告)日:2024-10-17

    申请号:US18641714

    申请日:2024-04-22

    申请人: Sonos, Inc.

    摘要: Embodiments described herein may involve queue versioning. An example implementation may involve a playback device initiating playback of a queue including one or more first audio streams. A queue identification token stored in data storage represents a current version of the queue. The playback device receives, from a computing system, data representing instructions to add one or more second audio streams to the queue, the instructions including an indication of the one or more second audio streams and a first token representing an expected queue version. The playback device determines whether the expected queue version represented by the first token matches the current version of the queue represented by the queue identification token. If not, the playback device foregoes adding the one or more second audio streams to the queue.

    Maintaining quality of service of non-volatile memory devices in heterogeneous environment

    公开(公告)号:US12112074B2

    公开(公告)日:2024-10-08

    申请号:US17706975

    申请日:2022-03-29

    发明人: Yaron Klein Oded Ilan

    IPC分类号: G06F12/00 G06F3/06

    摘要: In some arrangements, a manager of a storage system determines at least one abstracted memory structure for a tenant using a non-volatile memory of at least one non-volatile storage device. The abstracted memory structure includes at least one hardware storage unit of the non-volatile memory of the at least one non-volatile storage device. The at least one abstracted memory structure includes one or more of at least one virtual device corresponding to an application of the tenant or at least one domain corresponding to a volume of the application of the tenant. A virtual device mapping that maps the application of the tenant to the at least one hardware storage unit corresponding to the at least one virtual device is determined. A domain mapping that maps the volume to the at least one hardware storage unit corresponding to the at least one domain is determined.

    Combining xcopy's, unmaps, and writes in a single flush

    公开(公告)号:US12112039B2

    公开(公告)日:2024-10-08

    申请号:US18156683

    申请日:2023-01-19

    IPC分类号: G06F12/00 G06F3/06

    摘要: A technique for managing a log in a storage system includes adding descriptors to the log, the descriptors indicating changes in user data that affects metadata, and creating a working set of descriptors that includes both per-block descriptors for specifying per-block changes and per-extent descriptors for specifying per-extent changes, where an extent includes a range of contiguous blocks. The technique further includes flushing the working set in a single flush cycle, including flushing the per-block descriptors together with the per-extent descriptors.

    Methods for cache insertion using ghost lists

    公开(公告)号:US12105627B2

    公开(公告)日:2024-10-01

    申请号:US17650415

    申请日:2022-02-09

    发明人: Keyur B. Desai

    IPC分类号: G06F12/00 G06F12/0802

    CPC分类号: G06F12/0802 G06F2212/60

    摘要: A reverse cache for inserting data into a main cache is disclosed. The reverse cache is configured to identify candidates for insertion into a main cache. The reverse cache stores entries such as fingerprints and index values, which are representations of or that identify data. When the entry has been accessed multiple times or is a candidate for promotion based on operation of the reverse cache, data corresponding to the entry is promoted to the main cache.

    Memory block utilization in memory systems

    公开(公告)号:US12099734B2

    公开(公告)日:2024-09-24

    申请号:US17846761

    申请日:2022-06-22

    IPC分类号: G06F12/00 G06F3/06 G06F12/02

    摘要: Methods, systems, and devices for memory block utilization in memory systems are described. A system configured to allow a memory device to group or segment a memory block into two or more sub-memory blocks, which can be independently programmed is described herein. For example, a host system may determine a configuration of a memory array, and communicate the configuration information to the memory system, and transmit a command for an operation to the memory system. In some examples, the memory system may utilize the memory array configuration information and determine to segment the blocks of memory cells into sub-blocks. By segmenting the memory block into sub-blocks, the memory device may maintain its memory block density while supporting efficient programming of blocks of the memory array.

    Memory component with adjustable core-to-interface data rate ratio

    公开(公告)号:US12094565B2

    公开(公告)日:2024-09-17

    申请号:US17301089

    申请日:2021-03-24

    申请人: Rambus Inc.

    IPC分类号: G06F12/00 G11C7/10

    摘要: A memory component includes a memory bank comprising a plurality of storage cells and a data interface block configured to transfer data between the memory component and a component external to the memory component. The memory component further includes a plurality of column interface buses coupled between the memory bank and the data interface block, wherein a first column interface bus of the plurality of column interface buses is configured to transfer data between a first storage cell of the plurality of storage cells and the data interface block during a first access operation and wherein a second column interface bus of the plurality of column interface buses is configured to transfer the data between the first storage cell and the data interface block during a second access operation.