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    SOC-oriented concurrent test system for multiple clock domains and test method thereof
    1.
    发明授权
    SOC-oriented concurrent test system for multiple clock domains and test method thereof 有权

    公开(公告)号：US12130718B2

    公开(公告)日：2024-10-29

    申请号：US17801527

    申请日：2022-04-18

    申请人： Macrotest Semiconductor Inc.

    发明人： Guoliang Mao ,  Zhijie Bao

    IPC分类号： G06F11/273 ,  G01R31/317

    CPC分类号： G06F11/2733 ,  G01R31/31727

    摘要： The present disclosure relates to a System On Chip (SOC)-oriented concurrent test system and method for multiple clock domains, and belongs to the technical field of chip detection. A board system of the present disclosure includes a board, and a clock domain controller, a slot bus controller and a test subsystem which are arranged on the board; the clock domain controller is connected to the test subsystem and the slot bus controller; the slot bus controller is connected to a backplane bus; and the test subsystem includes a test processor and a signal processing unit; the test processor includes a test pattern memory, a memory control, a timing generator, a pattern generator and a command generator. In the present disclosure, by means of a concurrent test method for multiple clock domains, the test efficiency of a single SOC is improved, and the test cost of the single chip is also reduced, thus increasing the benefit. A higher coverage rate for detecting a failure of a chip that works in a concurrent working state of multiple modules is achieved, and the yield of chips after encapsulation is increased.

    Integrated circuit with timing correction circuitry
    2.
    发明授权
    Integrated circuit with timing correction circuitry 有权

    公开(公告)号：US12123911B1

    公开(公告)日：2024-10-22

    申请号：US18354925

    申请日：2023-07-19

    申请人： NXP USA, Inc.

    发明人： Shilpa Gupta ,  Rishi Bhooshan ,  Anis Mahmoud Jarrar ,  David Russell Tipple ,  Hadi Ahmadi Balef

    IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/3193

    CPC分类号： G01R31/318525 ,  G01R31/31727 ,  G01R31/31932

    摘要： A margin sensing circuit coupled to a flip flop of a critical data path includes a delay generator, a selector circuit which selects a delayed data output from the delay generator, a shadow latch corresponding to the flip flop, a comparator circuit which provides a match error indicator based on a comparison between a latched data output from the flip flop and a latched shadow output from the shadow latch, and an error latch to provide an error indicator based on the match error indicator. A correcting circuit includes a clock delay generator configured to receive a clock and provide a plurality of delayed clocks, and a clock selector circuit to select a delayed clock of the plurality of delayed clocks based on a set of clock select signals, in which each of the flip flop and the shadow latch are clocked by the selected delayed clock.

    METHODS AND SYSTEMS FOR REMOTE ACCESS HARDWARE TESTING
    4.
    发明公开
    METHODS AND SYSTEMS FOR REMOTE ACCESS HARDWARE TESTING 审中-公开

    公开(公告)号：US20240345158A1

    公开(公告)日：2024-10-17

    申请号：US18757076

    申请日：2024-06-27

    申请人： DISH Network L.L.C.

    发明人： Mansoor Ahmed ,  Hariprasanth Mohanraj

    IPC分类号： G01R31/28 ,  G01R31/317

    CPC分类号： G01R31/2896 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/31705

    摘要： The present disclosure is directed to methods and systems for remote access hardware testing. A user can remotely control probes connected to an oscilloscope to collect signal measurements of test points on a circuit board. The user can control the probe point position on the circuit board using an application on a device to enter the test point locations. In some implementations, a user controls the probe machine using remote controls and a camera video feed to identify the test points on the circuit board and capture measurements. The hardware testing system can automate the measurement process with a script or by using machine learning to identify test points via a camera, controlling the probe machine, and capturing measurements of the test point.

    Testing system and testing method
    8.
    发明授权
    Testing system and testing method 有权

    公开(公告)号：US12111353B2

    公开(公告)日：2024-10-08

    申请号：US18048437

    申请日：2022-10-20

    申请人： Realtek Semiconductor Corporation

    发明人： Shih-Hsuan Chiu ,  Meng-Che Li

    IPC分类号： G01R31/317 ,  H04L7/00 ,  H04L7/033

    CPC分类号： G01R31/31727 ,  G01R31/31726 ,  H04L7/0054 ,  H04L7/0331

    摘要： A testing system includes a signal generator circuit, a jitter modulation circuit, and an oscilloscope circuit. The signal generator circuit is configured to generate a clock pattern signal with a single clock pattern frequency. The jitter modulation circuit is configured to generate a jitter signal. A device-under-test is configured to receive an input signal. The input signal is a combination signal of the clock pattern signal and the jitter signal. The device-under-test includes a clock data recovery circuit and is further configured to generate an output signal according to the input signal. The oscilloscope circuit is configured to receive the output signal for determining performance of the clock data recovery circuit.

    Test devices, test systems, and operating methods of test systems
    10.
    发明授权
    Test devices, test systems, and operating methods of test systems 有权

    公开(公告)号：US12111351B2

    公开(公告)日：2024-10-08

    申请号：US17522188

    申请日：2021-11-09

    申请人： Samsung Electronics Co., Ltd.

    发明人： Ungjin Jang ,  Seonggwon Jang ,  Yongjeong Kim ,  Sooyong Park

    IPC分类号： G11C29/56 ,  G01R31/317 ,  G01R31/319 ,  G11C29/08

    CPC分类号： G01R31/31702 ,  G01R31/31905 ,  G11C29/08 ,  G11C29/56 ,  G11C2029/5602

    摘要： A test device configured to test a device under test (DUT) performing an interface of a pulse amplitude modulation (PAM) operation includes a logic generation/determination device configured to generate multiple bits corresponding to a test pattern, first and second drivers configured to generate respective first and second non return to zero (NRZ) signals according to a logic state of respective first and second bits among the multiple bits and output the respective generated first and second NRZ signals via respective first and second channels. The first NRZ signal has a first high level or a first low level according to the logic state of the first bit, and the second NRZ signal has a second high level or a second low level according to the logic state of the second bit. The first and second high levels are different from each other.