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公开(公告)号：US5675609A
公开(公告)日：1997-10-07
申请号：US451400
申请日：1995-05-26
Applicant: Raymond Edward Johnson
Inventor： Raymond Edward Johnson
Abstract: This contribution involves the generation, transmission, propagation and selective reception of electrical, magnetic or electromagnetic energy in the form of a halfwave sinusoidal pulse signal, from one location to another, whereby intelligence input for transmission is recovered from one sinusoidal pulse, or from a plurality of sinusoidal pulses. In a transmitter embodiment, one or more sinusoidal halfwave pulse generators are provided, where each pulse signal may be generated asynchronously, with varying polarity, duration and amplitude on a continuous serial sampled information basis. Complementary pulse signal filtering and recovering of transmitted intelligence is provided in a signal receiver embodiment. Another transmitter embodiment includes a software-driven signal synthesizing capability, wherein a plurality of timed sinusoidal halfways pulses are linearly summed as elementary signal components of an information-carrying propagable signal.
Abstract translation: 这一贡献涉及以半波正弦脉冲信号的形式从一个位置到另一个位置的电，磁或电磁能的产生，传输，传播和选择性接收，从而从一个正弦脉冲或从一个正弦脉冲中恢复用于传输的智能输入 多个正弦脉冲。 在发射机实施例中，提供一个或多个正弦半波脉冲发生器，其中每个脉冲信号可以以连续的串行采样信息为基础，以不同的极性，持续时间和幅度异步产生。 在信号接收机实施例中提供了传输智能的互补脉冲信号滤波和恢复。 另一个发射机实施例包括软件驱动信号合成能力，其中多个定时正弦中途脉冲作为信息携带可传播信号的基本信号分量被线性相加。
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公开(公告)号：US4245215A
公开(公告)日：1981-01-13
申请号：US41532
申请日：1979-05-22
Applicant: Lorne D. O'Connor , Richard Saylor , Stephen H. Buckser
Inventor： Lorne D. O'Connor , Richard Saylor , Stephen H. Buckser
CPC classification number: H04B3/542 , H04L27/24 , H04B2203/542
Abstract: A system for transmitting data from a transmitter to a receiver via an alternating current power line connecting the transmitter and receiver. The transmitter suppresses half cycles of the power signal, the suppressed half cycles being of alternating polarity. The data to be transmitted is represented by the time interval or number of power signal cycles between the suppressed half cycles.
Abstract translation: 一种用于经由连接发射机和接收机的交流电源线将数据从发射机发射到接收机的系统。 发射机抑制功率信号的半周期，抑制半周期是交替极性。 要发送的数据由抑制半周期之间的功率信号周期的时间间隔或数量表示。
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公开(公告)号：US4222035A
公开(公告)日：1980-09-09
申请号：US909502
申请日：1978-05-25
Applicant: Warren G. Lohoff
Inventor： Warren G. Lohoff
CPC classification number: H04L27/24 , H02J13/0048 , H04B3/542 , H04B2203/5408 , Y02B90/263 , Y02E60/7892 , Y04S40/123 , Y04S40/146 , Y10T307/477
Abstract: An electronic control circuit is disclosed herein for transmitting a coded signal and operating power to a selected one of a plurality of receivers via a single pair of wires. The control circuit includes a transmitter coupled to a source of AC line voltage and having a coding network for coding signals consisting of missing cycles from the AC line voltage so that a resultant output signal constitutes both the coded signal to the receiver and the operating power for the same receiver. Timing networks are included in the transmitter control circuit for allowing the output signals to be transmitted to the selected receiver only within a brief time interval. Reset networks are interconnected within the transmitter control circuit and the timing networks for returning the transmitter control circuit back to a condition of awaiting asynchronous commands for forwarding to a selected receiver via the single pair of wires.
Abstract translation: 本文公开了一种电子控制电路，用于经由一对导线将编码信号和操作功率发送到多个接收器中的所选择的一个。 控制电路包括耦合到AC线电压源的发射器，并且具有编码网络，用于编码由AC线电压引起的缺失周期组成的信号，使得合成输出信号构成接收机的编码信号和用于 相同的接收器。 定时网络包括在发射机控制电路中，用于仅在短时间间隔内将输出信号发送到所选择的接收机。 复位网络在发射机控制电路和定时网络内互连，用于使发射机控制电路返回到等待异步命令的条件，以经由单对线路转发到所选择的接收机。
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公开(公告)号：US4168397A
公开(公告)日：1979-09-18
申请号：US910168
申请日：1978-05-26
Applicant: Stevan D. Bradley
Inventor： Stevan D. Bradley
CPC classification number: H04L27/2071
Abstract: This 8-phase modulator comprises logic circuitry for converting tribits XYZ of input data into binary control signals D1, D2, D3 and D4 according to a prescribed plan, a pair of 4-phase signal generators responsive to associated pairs of control signals, and a signal source producing a pair of equal amplitude carrier signals of the same frequency and of phases which differ by 45.degree. for driving associated ones of the 4-phase generators 45.degree. out-of-phase. Equal amplitude vector signals from the two 4-phase generators are combined to produce a resultant vector signal which individually generates the phasors of an 8-phase signal set.
Abstract translation: 该8相调制器包括用于根据规定的平面将输入数据的三角形XYZ转换为二进制控制信号D1，D2，D3和D4的逻辑电路，响应于相关联的控制信号对的一对4相信号发生器，以及 信号源产生相同频率和相位的一对等幅载波信号，其相差45°，用于驱动45°异相的四相发生器中的相关联的相位。 来自两个4相发生器的等幅度矢量信号被组合以产生单独产生8相信号组的相量的合成矢量信号。
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公开(公告)号：US3943285A
公开(公告)日：1976-03-09
申请号：US359186
申请日：1973-05-10
Applicant: Robert Gordon Ragsdale , Henry Howard Parrish
Inventor： Robert Gordon Ragsdale , Henry Howard Parrish
CPC classification number: H04L27/2057 , H04L27/2338
Abstract: A data modem that operates to permit the concurrent high speed transmission/reception of digital data over two independent data links or systems, is disclosed. Data bits concurrently applied to a transmitting modem from two independent data sources are interlaced to form a stream of data bits that are effectively grouped as data words to be differentially phase modulated. Modulated data may be transmitted over ordinary voice grade telephone lines to a distant receiver modem at effectively twice the bit rate of the individual data sources. Successive groups of six interlaced data bits are divided into two groups of three bits which are uniquely identified by having a selected phase angle added to or subtracted from the differential phase angle for alternate groups of three bits. The selectively added phase angle is detected at a receiving modem to identify the respective groups of three bits and thereby permit accurate distribution of demodulated data bits to the respective data utilization terminals corresponding to the two data sources.
Abstract translation: 公开了一种用于允许通过两个独立的数据链路或系统同时高速发送/接收数字数据的数据调制解调器。 从两个独立数据源同时应用于发送调制解调器的数据位被隔行扫描以形成被有效地分组为待差分相位调制的数据字的数据位流。 调制数据可以通过普通语音级电话线路传输到远程接收机调制解调器，有效地是单个数据源的比特率的两倍。 六个隔行扫描数据位的连续组被分成两组三位，这两组通过对三位替代组的差分相位角加上或减去选定的相位角来唯一地标识。 在接收调制解调器处检测有选择地添加的相位角以识别三个比特的相应组，从而允许将解调的数据比特精确地分配到对应于两个数据源的各个数据利用终端。
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Patent Agency Ranking6.发明授权
公开(公告)号：US3643023A
公开(公告)日：1972-02-15
申请号：US3643023D
申请日：1968-03-01
Applicant: MILGO ELECTRONIC CORP
Inventor： RAGSDALE ROBERT G , PAYNE PAUL E
CPC classification number: H04L27/2057
Abstract: Digital data transmission at a very high bit rate through randomly selected voice-grade telephone lines by the use of a transmitter which includes digital differential angle modulation; and a receiver which includes digital differential angle demodulation is disclosed. Binary data wherein the individual bits are represented by a discrete level format during bit cell times is stored in multibit groups of randomly varying data patterns. Each multibit group is converted from its digital level format to a predetermined phase level format which includes a plurality of different phase, or angle, increments. At the transmitter a divider circuit receives a high-frequency signal which is many times higher than the bit rate of the data to be transmitted, and divides it into an intermediate frequency square wave signal which is still many times higher than the bit rate. The predetermined phase levels representative of each multibit group are compared with divider output taps by a comparison circuit which selectively alters the dividing operation so that an information-representing phase-shifted intermediate frequency signal is emitted. This information-representing phase-shifted signal is filtered and translated down to a low-frequency analog signal which is passed through a narrow band pass communication link exhibiting a linear phase over the band pass width. At the receiver end of the data communication system, the narrow band pass limited signal is translated up to the intermediate frequency and a clock signal is derived from the informationrepresenting envelope. This clock signal is employed to synchronously gate a high-frequency counter output into a detector circuit which samples a precise portion of a phaseshifted signal containing the information to be ascertained. Two separate storage registers in the detector circuit receive successive counter output valves depending upon the phase sampled from the precise portion of the information-containing signal. A parallel adder determines the difference between successive counts, each count of which is characteristic of the informationrepresenting phase change originally received during the interval in question. An encoder converts the phase-change signal as emitted by the parallel adder, back to its original digital data level format.
Abstract translation: 通过使用包括数字差分角度调制的发射机，通过随机选择的语音级电话线以非常高的比特率进行数字数据传输; 并且公开了包括数字差分角解调的接收机。 其中在比特单元时间期间各个比特由离散级格式表示的二进制数据被存储在随机变化的数据模式的多比特组中。 每个多位组从其数字电平格式转换成包括多个不同相位或角度增量的预定相位级格式。 在发射机处，分频器电路接收高于要发送的数据的比特率的高频信号，并将其分成比比特率高多倍的中频方波信号。 通过比较电路将表示每个多位组的预定相位电平与分频器输出抽头进行比较，该比较电路选择性地改变分频操作，从而发出表示信号的相移中频信号。 该信息表示相移信号被滤波并转换为低频模拟信号，该低频模拟信号通过在带通宽度上呈现线性相位的窄带通信通信链路。
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7.发明授权
公开(公告)号：US3638192A
公开(公告)日：1972-01-25
申请号：US3638192D
申请日：1970-07-06
Applicant: COLLINS RADIO CO
Inventor： RUTHERFORD KENNETH R , STRATHMAN LYLE R
IPC: H04B14/02 , H04L27/156 , H04Q9/00 , H04L27/14 , H04L27/24
CPC classification number: H04L27/1566 , H04B14/02 , H04L27/1563
Abstract: An asynchronous data to clock phase scripted shift register encoder and time/phase decoder circuit with clock phase information in the shift register in the form of two clock period wide pulses or one clock period wide pulses depending on the asynchronous data being either in phase or out of phase respectively with the clock. The system enables a reduction in shift register elements by a factor of 2 to 1, maximizes the decoder gate aperture, and the time decoder is capable of determining the correct delay to within one-half a clock period while a conventional shift register decoder does so only to within one clock period.
Abstract translation: 时钟相位脚本移位寄存器编码器和时间/相位解码器电路的异步数据，具有两个时钟周期宽脉冲形式的移位寄存器中的时钟相位信息或一个时钟周期宽脉冲，这取决于异步数据同相或异或 的相位分别与时钟。 该系统能够将移位寄存器元件减少2至1倍，使解码器门孔径最大化，并且时间解码器能够将传统的移位寄存器解码器这样做的时间周期内的正确延迟确定到半个时钟周期内 只能在一个时钟周期内。
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公开(公告)号：US3569626A
公开(公告)日：1971-03-09
申请号：US3569626D
申请日：1967-07-28
Applicant: KOKUSAI DENSHIN DENWA CO LTD
Inventor： MICHISHITA HISAKICHI , KAWAI KAZUO , SHINTANI SOTOKICHI
CPC classification number: H04L5/12
Abstract: A reference carrier wave synchronizing system for synchronizing a plurality of receiving reference waves with a plurality of transmitted, phase-modulated telegraphic waves having harmonic frequencies of a standard low frequency and each assuming 2n quantum phase positions in accordance with the number n of telegraph channels to be transmitted on each of the telegraphic waves; where the said synchronization is performed by compensating separately the fluctuations of instantaneous phase positions of the transmitted, phase-modulated waves caused in transmission medium and caused from the deviation in the phase or frequency of the standard low frequency.
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9.发明授权Synchronization of receiver time base in plural frequency differential phase shift system 失效接收机时基在同步差分相位移相系统中的同步
公开(公告)号：US3447085A
公开(公告)日：1969-05-27
申请号：US3447085D
申请日：1965-01-04
Applicant: GEN DYNAMICS CORP
Inventor： HAAS THIJS DE , GRAY MARTIN B , WELSH JOSEPH P
CPC classification number: H04L27/2662 , H04L5/0005 , H04L5/0048 , H04L7/08 , H04L27/261 , H04L27/2679 , H04L2007/047
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公开(公告)号：US2293507A
公开(公告)日：1942-08-18
申请号：US22625938
申请日：1938-08-23
Applicant: ERICH HUDEC
Inventor： ERICH HUDEC
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