公开(公告)号：US07045424B2

公开(公告)日：2006-05-16

申请号：US10903967

申请日：2004-07-30

Applicant: Ki-Chul Kim ,  Jin-Hee Kim ,  Sung-Ho Kim ,  Geum-Jong Bae

Inventor： Ki-Chul Kim ,  Jin-Hee Kim ,  Sung-Ho Kim ,  Geum-Jong Bae

IPC: H01L29/336 ,  H01L29/3205 ,  H01L29/4763 ,  H01L29/302

CPC classification number: H01L27/11568 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/792

Abstract: There is provided a method of fabricating a local SONOS type gate structure and a method of fabricating a nonvolatile memory cell having the same. The method includes forming a gate dielectric layer on a semiconductor substrate. A gate pattern, including a gate electrode and a hard mask layer pattern which are sequentially stacked, is formed on the gate dielectric layer. Then, a recess is formed on the boundary of the gate pattern and the gate dielectric layer. The recess is formed on one side wall of the gate pattern, and is prevented from forming on the other side wall of the gate pattern. A tunnel layer and a trapping dielectric layer are sequentially formed on substantially the entire surface of the semiconductor substrate having the recess formed thereon to fill the recess. At least a portion of the trapping dielectric layer is formed inside the recess.

Abstract translation: 提供了制造本地SONOS型栅极结构的方法以及制造具有该栅极结构的非易失性存储单元的方法。 该方法包括在半导体衬底上形成栅极电介质层。 在栅极电介质层上形成包括依次层叠的栅电极和硬掩模层图案的栅极图案。 然后，在栅极图案和栅极介电层的边界上形成凹部。 凹部形成在栅极图案的一个侧壁上，并且防止在栅极图案的另一个侧壁上形成。 隧道层和俘获电介质层依次形成在其上形成有凹部的半导体衬底的基本上整个表面上以填充凹部。 在凹陷内部形成有至少一部分捕获电介质层。

公开(公告)号：US07037787B2

公开(公告)日：2006-05-02

申请号：US11059475

申请日：2005-02-16

Applicant: Der-Tsyr Fan ,  Jung-Chang Lu ,  Chiou-Feng Chen ,  Prateep Tuntasood

Inventor： Der-Tsyr Fan ,  Jung-Chang Lu ,  Chiou-Feng Chen ,  Prateep Tuntasood

IPC: H01L29/336

CPC classification number: H01L27/115 ,  G11C16/0433 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825

Abstract: Flash memory and process of fabrication in which memory cells are formed with select gates in trenches between stacked, self-aligned floating and control gates, with buried source and drain regions which are gated by the select gates. Erase paths are formed between projecting rounded edges of the floating gates and the select gates, and programming paths extend from the mid-channel regions between the select gates and floating gates through the gate oxide to the edges of the floating gates. Trenched select gates can be provided on one or both sides of the floating and control gates, depending upon array architecture, and the stacked gates and dielectric covering them are used as a self-aligned mask in etching the substrate and other materials to form the trenches.

Abstract translation: 闪存和制造过程，其中在堆叠的，自对准的浮动和控制栅极之间的沟槽中用选择栅极形成存储器单元，其中由选择栅极选通的掩埋的源极和漏极区域。 擦除路径形成在浮动栅极和选择栅极的突出的圆形边缘之间，并且编程路径从选择栅极之间的中间沟道区域和通过栅极氧化物的浮动栅极延伸到浮动栅极的边缘。 根据阵列结构，可以在浮动和控制栅极的一侧或两侧设置倾斜的选择栅极，并且在蚀刻衬底和其它材料以形成沟槽时将堆叠的栅极和覆盖它们的电介质用作自对准掩模 。

公开(公告)号：US07190019B2

公开(公告)日：2007-03-13

申请号：US11013593

申请日：2004-12-14

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L29/787 ,  H01L29/788 ,  H01L29/336

CPC classification number: H01L27/11526 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/11529

Abstract: A widened contact area (170X) of a conductive feature (170) is formed by means of self-alignment between an edge (170E2) of the conductive feature and an edge (140E) of another feature (140). The other feature (“first feature”) is formed from a first layer, and the conductive feature is formed from a second layer overlying the first layer. The edge (170E2) of the conductive feature is shaped to provide a widened contact area. This shaping is achieved in a self-aligned manner by shaping the corresponding edge (140E) of the first feature.

Abstract translation: 通过在导电特征的边缘（170E2）与另一特征（140）的边缘（140E）之间的自对准，形成导电特征（170）的加宽的接触区域（170×）。 另一特征（“第一特征”）由第一层形成，并且导电特征由覆盖第一层的第二层形成。 导电特征的边缘（170E 2）成形为提供加宽的接触面积。 通过使第一特征的对应边缘（140E）成形，以自对准的方式实现该成形。

公开(公告)号：US07018881B2

公开(公告)日：2006-03-28

申请号：US10982730

申请日：2004-11-03

Applicant: Christoph Wasshuber

Inventor： Christoph Wasshuber

IPC: H01L29/8238 ,  H01L29/336 ,  H01L29/3205

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C23/00 ,  G11C2213/17 ,  G11C2216/08 ,  H01L29/7613 ,  Y10S977/937

Abstract: The present invention provides a single-electron transistor device (100). The device (100) comprises a source (105) and drain (110) located over a substrate (115) and a quantum island (120) situated between the source and drain (105, 110), to form tunnel junctions (125, 130) between the source and drain (105, 110). The device (100) further includes a movable electrode (135) located adjacent the quantum island (120) and a displaceable dielectric (140) located between the moveable electrode (135) and the quantum island (120). The present invention also includes a method of fabricating a single-electron device (200), and a transistor circuit (300) that include a single-electron device (310).

Abstract translation: 本发明提供一种单电子晶体管器件（100）。 设备（100）包括位于衬底（115）上的源极（105）和漏极（110）以及位于源极和漏极（105,110）之间的量子岛（120），以形成隧道结（125,130） ）在源极和漏极（105,110）之间。 装置（100）还包括位于量子岛（120）附近的可移动电极（135）和位于可动电极（135）和量子岛（120）之间的位移电介质（140）。 本发明还包括制造单电子器件（200）的方法和包括单电子器件（310）的晶体管电路（300）。