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公开(公告)号：US09870044B2
公开(公告)日：2018-01-16
申请号：US15280057
申请日：2016-09-29
Applicant: Intel Corporation
Inventor： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
IPC: G06F1/32 , G06F12/08 , G06F11/14 , G06F12/084 , G06F12/0875 , G11C7/10 , G06F9/44
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
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公开(公告)号：US09846464B2
公开(公告)日：2017-12-19
申请号：US14794872
申请日：2015-07-09
Applicant: LITE-ON TECHNOLOGY CORPORATION
Inventor： Zih-Min Yang , Ting-Hsi Huang
CPC classification number: G06F1/263 , G01R21/06 , G01R31/42 , G06F1/3206 , H02J1/10 , H02J9/005 , Y10T307/391 , Y10T307/582 , Y10T307/707 , Y10T307/724 , Y10T307/729
Abstract: The instant disclosure provides a power supply system and control method thereof. The power supply system comprises at least two power supplies electrically coupled in parallel. The control unit of the power supply generates a wake-up signal or a sleep signal according to the loading status. A second communication port of each power supply is coupled to a first communication port of the next stage power supply to establish cascading communications architecture. The first communication port receives a wake-up signal from the second communication port of the previous stage power supply and outputs a sleep signal to the second communication port of the previous stage power supply. The second communication port receives the sleep signal from the first communication port of the next stage power supply and outputs the wake-up signal to the first communication port of the next stage power supply.
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公开(公告)号：US09141180B2
公开(公告)日：2015-09-22
申请号：US14630909
申请日：2015-02-25
Applicant: Intel Corporation
Inventor： Sanjeev Jahagirdar , Varghese George , John Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
IPC: G06F1/32
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
Abstract translation: 本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。 处理器可以包括专用高速缓存存储器。 电压调节器可以耦合到处理器以向处理器提供工作电压。 在处理器转换到零电压电源管理状态期间，电压调节器施加到处理器的工作电压可以减小到大约零，并且与处理器相关联的状态变量可以被保存到专用高速缓冲存储器。
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公开(公告)号：US20150052377A1
公开(公告)日：2015-02-19
申请号：US14496233
申请日：2014-09-25
Applicant: Intel Corporation
Inventor： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
IPC: G06F1/32
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
Abstract translation: 本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。 处理器可以包括专用高速缓存存储器。 电压调节器可以耦合到处理器以向处理器提供工作电压。 在处理器转换到零电压电源管理状态期间，电压调节器施加到处理器的工作电压可以减小到大约零，并且与处理器相关联的状态变量可以被保存到专用高速缓冲存储器。
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5.发明授权公开(公告)号：US08928259B2
公开(公告)日：2015-01-06
申请号：US13307191
申请日：2011-11-30
Applicant: Viswanathan Kanakasabai , Bhaskar Sen
Inventor： Viswanathan Kanakasabai , Bhaskar Sen
IPC: H02P3/14
CPC classification number: H02P27/06 , B60L11/005 , B60L11/1853 , B60L11/1866 , B60L11/1868 , B60L15/007 , B60L2210/10 , B60L2240/54 , B60Y2300/91 , B60Y2400/112 , H02P27/14 , H05K13/00 , Y02T10/644 , Y02T10/645 , Y02T10/7005 , Y02T10/7022 , Y02T10/7061 , Y02T10/7066 , Y10T29/49117 , Y10T307/582 , Y10T307/707
Abstract: A modular stacked DC architecture for traction system includes a propulsion system includes an electric drive, a direct current (DC) link electrically coupled to the electric drive, and a first DC-DC converter coupled to the DC link. A first energy storage device (ESD) is electrically coupled to the first DC-DC converter, and a second DC-DC converter is coupled to the DC link and to the first DC-DC converter. The system also includes a second energy storage device electrically coupled to the second DC-DC converter and a controller coupled to the first and second DC-DC converters and configured to control a transfer of energy between the first ESD and the DC link via the first and second DC-DC converters.
Abstract translation: 用于牵引系统的模块化堆叠DC架构包括推进系统，其包括电驱动器，电耦合到电驱动器的直流（DC）连接器和耦合到DC链路的第一DC-DC转换器。 第一能量存储装置（ESD）电耦合到第一DC-DC转换器，并且第二DC-DC转换器耦合到DC链路和第一DC-DC转换器。 该系统还包括电耦合到第二DC-DC转换器的第二能量存储装置和耦合到第一和第二DC-DC转换器并被配置为经由第一DC-DC转换器控制第一ESD和DC链路之间的能量传递的控制器 和第二DC-DC转换器。
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Patent Agency Ranking
公开(公告)号：US20150006938A1
公开(公告)日：2015-01-01
申请号：US14254413
申请日：2014-04-16
Applicant: Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
Inventor： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
IPC: G06F1/32
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
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公开(公告)号：US08884563B2
公开(公告)日：2014-11-11
申请号：US13309503
申请日：2011-12-01
Applicant: John Berkheimer , Jerry Fan , Jianchu Zheng
Inventor： John Berkheimer , Jerry Fan , Jianchu Zheng
CPC classification number: H02P6/16 , H02J1/102 , H02P27/08 , H02P29/026 , Y10T307/406 , Y10T307/582 , Y10T307/74
Abstract: A renewable energy source is converted into a desired DC voltage that is delivered to a DC motor controller of a permanent magnet motor. A micro controller monitors the amount of supplied renewable DC having the desired DC voltage, which is delivered to each phase of the motor by turning on FET switches on demand. If the renewable DC available at a given instant is not adequate to power a particular phase of the motor, then the micro controller turns on backup FET switches that are part of an independent drive circuit that is in parallel with drive circuits of the renewable DC power circuit, to deliver to the motor line DC, which is produced from an AC supply that has gone through an AC to DC converter. Once charged, the renewable DC power will power the next available phase of the motor.
Abstract translation: 可再生能源被转换成期望的直流电压，其被输送到永磁电动机的直流电动机控制器。 微控制器通过根据需要开启FET开关来监控具有所需直流电压的供应的可再生DC的量，该直流电压被传送到电动机的每个相。 如果在给定时刻可再生的DC可用性不足以为电动机的特定阶段供电，则微控制器接通作为与可再生DC电源的驱动电路并联的独立驱动电路的一部分的备用FET开关 电路，传送到通过AC到DC转换器的AC电源产生的电动机线DC。 一旦充电，可再生的直流电源将为电机的下一个可用阶段供电。
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公开(公告)号：US20140310544A1
公开(公告)日：2014-10-16
申请号：US14254422
申请日：2014-04-16
Applicant: Jose Allarey , Sanjeev Jahagirdar
Inventor： Jose Allarey , Sanjeev Jahagirdar
IPC: G06F1/32
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A voltage regulator may be coupled to a processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero while an external voltage is continuously applied to a portion of the processor to save state variables of the processor during the zero voltage management power state.
Abstract translation: 本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。 电压调节器可以耦合到处理器以向处理器提供工作电压。 在向处理器转换到零电压电源管理状态期间，由电压调节器施加到处理器的工作电压可以减小到大约为零，同时外部电压被持续地施加到处理器的一部分以保存处理器的状态变量 处理器在零电压管理电源状态。
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公开(公告)号：US08707066B2
公开(公告)日：2014-04-22
申请号：US13149873
申请日：2011-05-31
Applicant: Jose Allarey , Sanjeev Jahagirdar
Inventor： Jose Allarey , Sanjeev Jahagirdar
IPC: G06F1/00 , G06F1/26 , H02J1/00 , H02J3/00 , F02P3/02 , H02M3/18 , H02M7/08 , H02M7/5383 , G11C11/14
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A voltage regulator may be coupled to a processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero while an external voltage is continuously applied to a portion of the processor to save state variables of the processor during the zero voltage management power state.
Abstract translation: 本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。 电压调节器可以耦合到处理器以向处理器提供工作电压。 在向处理器转换到零电压电源管理状态期间，由电压调节器施加到处理器的工作电压可以减小到大约为零，同时外部电压被持续地施加到处理器的一部分以保存处理器的状态变量 处理器在零电压管理电源状态。
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公开(公告)号：US08552692B2
公开(公告)日：2013-10-08
申请号：US13078254
申请日：2011-04-01
Applicant: Ria Ju , Young-Hak Pyo , Sergey Vasichev , Seung-Hyuck Paek , Sang-Chul Seo
Inventor： Ria Ju , Young-Hak Pyo , Sergey Vasichev , Seung-Hyuck Paek , Sang-Chul Seo
CPC classification number: H02J7/0072 , H02M3/1588 , H02M2001/0077 , Y02B40/90 , Y02B70/1466 , Y10T307/582 , Y10T307/625 , Y10T307/707
Abstract: A charger and discharger for a secondary battery includes a secondary battery coupled to an output stage of the charger and discharger, a first converter circuit including a first pulse voltage generator that outputs a first pulse voltage according to a first duty ratio, and a first inductor that outputs a first current in proportion to a value of an integral of the outputted first pulse voltage with respect to time to a positive electrode terminal of the secondary battery, a second converter circuit including a second pulse voltage generator that outputs a second pulse voltage according to a second duty ratio, and a second inductor that outputs a second current in proportion to a value of an integral of the outputted second pulse voltage with respect to time to a negative electrode terminal of the secondary battery, and first and second controllers controlling the duty ratios of the first and second pulse voltage generators, respectively.
Abstract translation: 一种用于二次电池的充电器和放电器包括耦合到充电器和放电器的输出级的二次电池，包括根据第一占空比输出第一脉冲电压的第一脉冲电压发生器和第一电感器的第一转换器电路 其输出与所输出的第一脉冲电压的积分值相对于二次电池的正极端子的比例的第一电流;第二转换器电路，包括：第二脉冲电压发生器，其输出第二脉冲电压， 以及第二电感器，其将与所输出的第二脉冲电压的积分值成比例地相对于二次电池的负极端子输出第二电流，以及控制该第二电容器的第一和第二控制器 第一和第二脉冲电压发生器的占空比分别为。
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