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11 条记录 (耗时 0.017 秒)

    Fet-teld combination with capacitively coupled output electrode means
    2.
    发明授权
    Fet-teld combination with capacitively coupled output electrode means 失效
    与电容耦合的输出电极装置进行组合

    公开(公告)号：US4145624A

    公开(公告)日：1979-03-20

    申请号：US816692

    申请日：1977-07-18

    申请人： Lakshminarasimha C. Upadhyayula

    发明人： Lakshminarasimha C. Upadhyayula

    IPC分类号： H01L27/26 ,  H03K3/357 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/10 ,  H03K19/08 ,  H03K19/40

    CPC分类号： H01L27/265 ,  H03K19/017 ,  H03K19/018507 ,  H03K19/10 ,  H03K3/357

    摘要： A field effect transistor (FET) is connected in series to a transferred electron logic device (TELD), the TELD being a non-linear load resistor for the FET. The current thresholding property of the TELD and the saturation characteristics of the FET are utilized to produce an output pulsed signal of substantial voltage gain with fast rise time and short pulse width. An output electrode is capacitively coupled to the TELD to provide an output pulsed signal of alternating polarity for direct interconnection of devices in cascaded circuits.

    摘要翻译： 场效应晶体管（FET）与转移的电子逻辑器件（TELD）串联连接，TELD是用于FET的非线性负载电阻。 TELD的电流阈值特性和FET的饱和特性用于产生具有快速上升时间和短脉冲宽度的实质电压增益的输出脉冲信号。 输出电极电容耦合到TELD，以提供具有交替极性的输出脉冲信号，用于级联电路中的器件的直接互连。

    Planar transferred electron logic device
    3.
    发明授权
    Planar transferred electron logic device 失效
    平面转移电子逻辑器件

    公开(公告)号：US3991328A

    公开(公告)日：1976-11-09

    申请号：US589855

    申请日：1975-06-24

    申请人： Chainulu Lakshminarasimha Upadhyayula

    发明人： Chainulu Lakshminarasimha Upadhyayula

    IPC分类号： H01L47/00 ,  H03K3/357 ,  H03K3/26 ,  H01L27/26 ,  H03F1/36

    CPC分类号： H03K3/357 ,  H01L47/00

    摘要： A planar transferred electron device is biased such that the voltage across the anode and cathode electrodes is above that of a threshold voltage in the presence of which the device is characterized by a transfer of electrons from a high to a low mobility sub-band and the formation of domains. A reverse biasing potential is applied between the gate and cathode electrodes which is of sufficient magnitude to cause in the quiescent state the suppression of the formation of these domains. When signals above a given level are provided between the gate and cathode electrodes, the device operates according to a transferred electron effect including the formation of the domains.

    摘要翻译： 平面转移的电子器件被偏置，使得阳极和阴极电极两端的电压高于阈值电压的电压，器件的特征在于电子从高迁移率子载波子带传递到低迁移率子带， 形成域。 在栅电极和阴极电极之间施加反向偏置电位，其具有足够的量级，从而在静止状态下抑制这些畴的形成。 当在栅极和阴极之间提供高于给定电平的信号时，器件根据包括形成畴的转移的电子效应进行工作。

    METAL-INSULATOR TRANSITION LATCH
    6.
    发明申请
    METAL-INSULATOR TRANSITION LATCH 有权
    金属绝缘子过渡锁

    公开(公告)号：US20130106480A1

    公开(公告)日：2013-05-02

    申请号：US13362538

    申请日：2012-01-31

    申请人： Gilberto Medeiros Ribeiro ,  Matthew D. Pickett ,  R. Stanley Williams

    发明人： Gilberto Medeiros Ribeiro ,  Matthew D. Pickett ,  R. Stanley Williams

    IPC分类号： H03K3/335

    CPC分类号： H01L45/146 ,  G11C13/0007 ,  G11C2211/5614 ,  G11C2213/15 ,  H01L45/04 ,  H01L45/1233 ,  H03K3/357

    摘要： A metal-insulator transition (MIT) latch includes a first electrode spaced apart from a second electrode and an MIT material disposed between said first and second electrodes. The MIT material comprises a negative differential resistance (NDR) characteristic that exhibits a discontinuous resistance change at a threshold voltage or threshold current. Either the first or second electrode is electrically connected to an electrical bias source regulated to set a resistance phase of the MIT material.

    摘要翻译： 金属 - 绝缘体转变（MIT）锁存器包括与第二电极间隔开的第一电极和设置在所述第一和第二电极之间的MIT材料。 MIT材料包括在阈值电压或阈值电流下呈现不连续电阻变化的负差分电阻（NDR）特性。 第一或第二电极电连接到被调节以设定MIT材料的电阻相位的电偏压源。

    Periodic waveform generating circuit
    8.
    发明授权
    Periodic waveform generating circuit 失效
    周期波形发生电路

    公开(公告)号：US5770958A

    公开(公告)日：1998-06-23

    申请号：US831995

    申请日：1997-04-01

    申请人： Kunihiro Arai ,  Hideaki Matsuzaki

    发明人： Kunihiro Arai ,  Hideaki Matsuzaki

    IPC分类号： H03K3/313 ,  H03K3/356 ,  H03K3/357 ,  H03K3/36 ,  H03K17/56 ,  H03K19/08 ,  H03B19/00 ,  H03K17/70

    CPC分类号： H03K3/356 ,  H03K3/357 ,  H03K3/36

    摘要： A first partial circuit is formed by grounding the emitter electrode of a first negative differential resistive element, connecting the emitter electrode of a second negative differential resistive element to the collector electrode of the first negative differential resistive element, and connecting a first field-effect transistor in parallel with the first negative differential resistive element. A second partial circuit is formed by grounding the emitter electrode of a third negative differential resistive element, connecting the emitter electrode of a fourth negative differential resistive element to the collector electrode of the third negative differential resistive element, and connecting a second field-effect transistor in parallel with the third negative differential resistive element. An output from the first partial circuit is input to the input of the second partial circuit. The inversion of the output of the second partial circuit is input to the input of the first partial circuit. A clock signal and a signal whose phase is opposite to that of the clock signal are applied to the collector electrodes of the second and fourth negative differential resistive elements, respectively. A frequency-divided signal of the clock signal is output from each partial circuit.

    摘要翻译： 第一部分电路是通过将第一负差分电阻元件的发射电极与第一负差分电阻元件的发射电极连接到第一负差分电阻元件的集电极并将第一场效应晶体管 与第一负差分电阻元件并联。 通过将第三负差分电阻元件的发射电极与第三负差分电阻元件的发射极连接到第三负差分电阻元件的集电极，并将第二场效应晶体管连接起来形成第二部分电路 与第三负差分电阻元件并联。 来自第一部分电路的输出被输入到第二部分电路的输入端。 第二部分电路的输出的反相输入到第一部分电路的输入端。 时钟信号和与时钟信号的相位相反的信号分别被施加到第二和第四负差分电阻元件的集电极。 从每个部分电路输出时钟信号的分频信号。

    Pulse train generator
    9.
    发明授权
    Pulse train generator 失效
    脉冲发电机

    公开(公告)号：US4158784A

    公开(公告)日：1979-06-19

    申请号：US862191

    申请日：1977-12-19

    申请人： Walter R. Curtice

    发明人： Walter R. Curtice

    IPC分类号： H03K3/357 ,  H03K3/64

    CPC分类号： H03K3/357

    摘要： A pulse train generator operating at subnanosecond periods includes a transferred-electron device (TED) in series with an open circuited resonant transmission line. The transmission line sustains domain formation in the TED. A filter coupled to the TED may be utilized to produce pulses at a subharmonic of the TED transit time frequency, determined by the length of the transmission line.

    摘要翻译： 在亚纳秒时段运行的脉冲串发生器包括与开路谐振传输线串联的转移电子器件（TED）。 传输线支持TED中的域形成。 耦合到TED的滤波器可以用于以由传输线的长度确定的TED通过时间频率的次谐波产生脉冲。

    Transferred electron device pulse train generator
    10.
    发明授权
    Transferred electron device pulse train generator 失效
    转移电子装置脉冲发电机

    公开(公告)号：US4000415A

    公开(公告)日：1976-12-28

    申请号：US656286

    申请日：1976-02-09

    申请人： Walter Richard Curtice

    发明人： Walter Richard Curtice

    IPC分类号： H03K3/357 ,  H03K3/64 ,  H03K5/01

    CPC分类号： H03K3/357 ,  H03K3/64

    摘要： A controlled interval pulse train generator comprising a plurality of three terminal transferred electron logic devices, and a delay line. The generator produces a train of small pulse-width voltage pulses at intervals determined by the delay line. The pulse train is started in response to an initial pulse and is terminated in response to a voltage step.

    摘要翻译： 一种受控间隔脉冲串发生器，包括多个三端转移电子逻辑器件和延迟线。 该发生器以延迟线确定的间隔产生一列小脉冲宽度的电压脉冲。 响应于初始脉冲启动脉冲串，并响应于电压步骤终止脉冲序列。