公开(公告)号：US09990302B2

公开(公告)日：2018-06-05

申请号：US15163682

申请日：2016-05-25

申请人： National Chiao Tung University

发明人： Tien-Fu Chen ,  Meng-Fan Chang ,  Keng-Hao Yang

IPC分类号： G06F12/0897 ,  G06F12/0891 ,  G06F12/1009

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0891 ,  G06F12/1009 ,  G06F2212/1021 ,  G06F2212/2228 ,  G06F2212/60

摘要： A tag memory and a cache system with automating tag comparison mechanism and a cache method thereof are provided. The tag memory in the cache system includes a memory cell array, sensing amplifiers and a tag comparison circuit. The memory cell array stores cache tags, and outputs row tags of the cache tags according to an index in a memory address. The sensing amplifiers perform signal amplifications on the row tags to serve as comparison tags. The tag comparison circuit performs parallel comparisons between a target tag in the memory address and the row tags. When one of the row tags matches the target tag, the tag comparison circuit outputs a location of the matched row tag to serve as a first column address. The first column address is a column address where the memory address corresponds to a first data memory in the cache system.

公开(公告)号：US20150317093A1

公开(公告)日：2015-11-05

申请号：US14762039

申请日：2013-12-24

申请人： HITACHI, LTD.

发明人： Naoya OKADA ,  Yusuke NONAKA ,  Akihiko ARAKI ,  Shintaro KUDO ,  Makio MIZUNO

IPC分类号： G06F3/06 ,  G06F12/08

CPC分类号： G06F3/0619 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0638 ,  G06F12/08 ,  G06F12/0868 ,  G06F12/0875 ,  G06F12/0893 ,  G06F2212/222 ,  G06F2212/2228 ,  Y02D10/13

摘要： A storage controller has a processor, a volatile first cache memory that is coupled to the processor and that temporarily stores data, a nonvolatile second cache memory that is coupled to a microprocessor and that temporarily stores data, and a battery that is configured to supply electrical power to at least the processor and the first cache memory when a power stoppage has occurred. The second cache memory includes a dirty data area for storing dirty data, which is data that is not stored in the storage device, and a remaining area other than the dirty data area. When a power stoppage has occurred, the processor stores as target data in the remaining area of the second cache memory either all or a part of the data stored in the first cache memory.

摘要翻译： 存储控制器具有处理器，耦合到处理器并临时存储数据的易失性第一高速缓冲存储器，耦合到微处理器并临时存储数据的非易失性第二高速缓冲存储器，以及被配置为提供电气的电池 当发生停电时，至少将处理器和第一高速缓存存储器供电。 第二高速缓冲存储器包括用于存储不存储在存储装置中的数据的脏数据区域和除脏数据区域以外的剩余区域的脏数据区域。 当发生停电时，处理器将存储在第一高速缓冲存储器中的全部或一部分数据作为目标数据存储在第二高速缓冲存储器的剩余区域中。

公开(公告)号：US09009417B2

公开(公告)日：2015-04-14

申请号：US12934037

申请日：2010-08-27

申请人： Tomoaki Okawa

发明人： Tomoaki Okawa

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F1/32 ,  G06F11/14 ,  G06F13/00 ,  G06F13/28 ,  G06F11/20

CPC分类号： G06F12/0804 ,  G06F1/3212 ,  G06F1/3275 ,  G06F11/1441 ,  G06F11/201 ,  G06F11/2015 ,  G06F11/2089 ,  G06F12/0866 ,  G06F2212/2228 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/174

摘要： It is an object to improve a reliability of a data protection for a storage control apparatus that is provided with a redundant configuration that is made of a plurality of clusters.A memory unit in each of the clusters C1 and C2 is provided with a first memory 3 having a volatile property, a battery 5 that is configured to supply an electrical power to the first memory 3, and a second memory 4 that stores data that is transferred from the first memory 3 in the case of a power outage. A control unit selects an operating mode for protecting data from a normal mode, a write through mode, and an access disable mode (a not ready state) based on a remaining power level of the battery 5.

摘要翻译： 本发明的目的是提高具有由多个集群构成的冗余配置的存储控制装置的数据保护的可靠性。 集群C1和C2中的每一个中的存储器单元设置有具有易失性的第一存储器3，被配置为向第一存储器3提供电力的电池5和存储数据的第二存储器4 在断电的情况下从第一存储器3传送。 控制单元基于电池5的剩余功率电平来选择用于保护数据的正常模式，写入模式和访问禁用模式（未就绪状态）的操作模式。

公开(公告)号：US08214610B2

公开(公告)日：2012-07-03

申请号：US12503242

申请日：2009-07-15

申请人： William Lomelino ,  Arindam Banerjee ,  Pradeep Radhakrishna Venkatesha ,  Jayaraj Rajappan

发明人： William Lomelino ,  Arindam Banerjee ,  Pradeep Radhakrishna Venkatesha ,  Jayaraj Rajappan

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0804 ,  G06F11/1441 ,  G06F12/0866 ,  G06F2212/2228 ,  Y02D10/13

摘要： A system includes a data storage device, a controller coupled with the data storage device, a backup device coupled with the controller for backing up a modified portion of data and volatile memory metadata stored by the controller, and a backup power source for powering the controller. The controller includes a pre-specified region of volatile memory for storing backup device metadata for managing a modified portion of data, the metadata comprising one or more intents corresponding to modified data written back to the data storage device. The controller is configured to invalidate the one or more intents. During a restore operation, the controller is configured to store the backup device metadata in the pre-specified region of volatile memory when a charge on the backup power source is at least a minimum threshold charge and to store the updated backup device metadata in the backup device during an interruption of power.

摘要翻译： 系统包括数据存储设备，与数据存储设备耦合的控制器，与控制器耦合的备用设备，用于备份由控制器存储的数据的修改部分和易失性存储器元数据;以及用于为控制器供电的备用电源 。 所述控制器包括用于存储用于管理修改的数据部分的备份设备元数据的易失性存储器的预定区域，所述元数据包括对应于被写回数据存储设备的修改数据的一个或多个意图。 控制器被配置为使一个或多个意图无效。 在还原操作期间，当备用电源的费用至少为最小阈值电荷并且将更新的备份设备元数据存储在备份中时，控制器被配置为将备份设备元数据存储在易失性存储器的预定区域内 设备在电源中断期间。

公开(公告)号：US07953774B2

公开(公告)日：2011-05-31

申请号：US12234411

申请日：2008-09-19

申请人： Shi Cong ,  Scott Brender ,  Karan Mehra ,  Darren G. Moss ,  William R. Tipton ,  Surendra Verma

发明人： Shi Cong ,  Scott Brender ,  Karan Mehra ,  Darren G. Moss ,  William R. Tipton ,  Surendra Verma

IPC分类号： G06F17/30

CPC分类号： G06F12/121 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0673 ,  G06F11/1435 ,  G06F11/1471 ,  G06F12/0638 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/221 ,  G06F2212/2228 ,  G11C7/1006

摘要： A method and a processing device are provided for sequentially aggregating data to a write log included in a volume of a random-access medium. When data of a received write request is determined to be suitable for sequentially aggregating to a write log, the data may be written to the write log and a remapping tree, for mapping originally intended destinations on the random-access medium to one or more corresponding entries in the write log, may be maintained and updated. At time periods, a checkpoint may be written to the write log. The checkpoint may include information describing entries of the write log. One or more of the checkpoints may be used to recover the write log, at least partially, after a dirty shutdown. Entries of the write log may be drained to respective originally intended destinations upon an occurrence of one of a number of conditions.

摘要翻译： 提供了一种方法和处理装置，用于将数据顺序地聚合到包括在随机存取介质的卷中的写入日志。 当接收到的写入请求的数据被确定为适合于顺序聚合到写入日志时，数据可被写入写入日志和重新映射树，用于将随机访问介质上的原始目的地映射到一个或多个相应的 写入日志中的条目可以被维护和更新。 在时间段，检查点可能被写入写日志。 检查点可以包括描述写入日志的条目的信息。 一个或多个检查点可用于在脏关闭后至少部分恢复写入日志。 在发生多个条件之一时，写入日志的条目可以被排放到相应的原始目的地。

公开(公告)号：US20060184736A1

公开(公告)日：2006-08-17

申请号：US11061187

申请日：2005-02-17

申请人： Michael Benhase ,  Matthew Kalos ,  Carol Spanel ,  Andrew Walls

发明人： Michael Benhase ,  Matthew Kalos ,  Carol Spanel ,  Andrew Walls

IPC分类号： G06F12/14

CPC分类号： G06F11/1441 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/2228 ,  G06F2212/282

摘要： An apparatus, system and method are disclosed for storing modified data. The apparatus includes a battery source for supplying backup power. The apparatus also includes a memory module for storing data. The memory module includes a backup portion and a non-backup portion. Only the backup portion is backed up by the battery source in the event of a power failure. A data flow module controls data flow into and out of the memory module. The data flow module stores modified data exclusively in the backup portion of the memory module.

摘要翻译： 公开了用于存储修改数据的装置，系统和方法。 该装置包括用于提供备用电力的电池源。 该装置还包括用于存储数据的存储器模块。 存储器模块包括备份部分和非备份部分。 如果电源出现故障，只有备份部分由电池源备份。 数据流模块控制进出存储器模块的数据流。 数据流模块将修改的数据专门存储在存储器模块的备份部分中。

公开(公告)号：US06957355B2

公开(公告)日：2005-10-18

申请号：US10247696

申请日：2002-09-18

申请人： John D. Acton ,  Mark Farabaugh ,  William M. Hamilton, III ,  Joel P. Miller ,  Jonathan Broome

发明人： John D. Acton ,  Mark Farabaugh ,  William M. Hamilton, III ,  Joel P. Miller ,  Jonathan Broome

IPC分类号： G06F11/14 ,  G06F12/08 ,  G06F10/14

CPC分类号： G06F11/1441 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/2228

摘要： A method and system for managing cache levels based on battery backup level are described. In one embodiment, the method comprises measuring the level of charge stored in an exhaustible power source. The method further comprises monitoring the level of charge stored in the exhaustible power source. The method further comprises adjusting the storage level of the cache in response to a detected change in the level of charge. In this way, the method ensures that adequate battery power is available to transfer the contents of the cache to a non-volatile data storage medium.

摘要翻译： 描述了基于电池备份级别来管理高速缓存级别的方法和系统。 在一个实施例中，该方法包括测量存储在可消耗电源中的电荷水平。 该方法还包括监视存储在可消耗电源中的电荷水平。 该方法还包括响应于检测到的电荷电平的变化来调整高速缓存的存储电平。 以这种方式，该方法确保足够的电池电力可用于将高速缓存的内容传送到非易失性数据存储介质。

公开(公告)号：US20180095884A1

公开(公告)日：2018-04-05

申请号：US15282478

申请日：2016-09-30

申请人： INTEL CORPORATION

发明人： Maciej KAMINSKI ,  Piotr WYSOCKI ,  Slawomir PTAK

IPC分类号： G06F12/0873 ,  G06F3/06 ,  G06F12/0804 ,  G06F12/0868

CPC分类号： G06F12/0873 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/068 ,  G06F12/0804 ,  G06F12/0868 ,  G06F2212/1024 ,  G06F2212/205 ,  G06F2212/221 ,  G06F2212/2228 ,  G06F2212/224 ,  G06F2212/271 ,  G06F2212/284 ,  G06F2212/3042 ,  G06F2212/305 ,  G06F2212/313

摘要： An apparatus is described. The apparatus includes a memory controller comprising logic circuitry to implement a mass storage cache in a non volatile region of a system memory. The non volatile region of the system memory is to support execution of program code directly out of the non volatile region system memory.

公开(公告)号：US20170220480A1

公开(公告)日：2017-08-03

申请号：US15163682

申请日：2016-05-25

申请人： National Chiao Tung University

发明人： Tien-Fu Chen ,  Meng-Fan Chang ,  Keng-Hao Yang

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/0897 ,  G06F12/0846 ,  G06F12/0891 ,  G06F12/1009 ,  G06F2212/1021 ,  G06F2212/2228 ,  G06F2212/60

摘要： A tag memory and a cache system with automating tag comparison mechanism and a cache method thereof are provided. The tag memory in the cache system includes a memory cell array, sensing amplifiers and a tag comparison circuit. The memory cell array stores cache tags, and outputs row tags of the cache tags according to an index in a memory address. The sensing amplifiers perform signal amplifications on the row tags to serve as comparison tags. The tag comparison circuit performs parallel comparisons between a target tag in the memory address and the row tags. When one of the row tags matches the target tag, the tag comparison circuit outputs a location of the matched row tag to serve as a first column address. The first column address is a column address where the memory address corresponds to a first data memory in the cache system.

公开(公告)号：US20160188456A1

公开(公告)日：2016-06-30

申请号：US14587325

申请日：2014-12-31

申请人： ATI Technologies ULC ,  Advanced Micro Devices, Inc.

发明人： Sergey Blagodurov ,  Gabriel H. Loh ,  Mauricio Breternitz

IPC分类号： G06F12/02 ,  G06F12/12 ,  G06F9/54 ,  G11C14/00 ,  G11C11/34 ,  G06F12/06 ,  G06F12/08

CPC分类号： G06F9/48 ,  G06F12/0238 ,  G06F12/0811 ,  G06F2212/205 ,  G06F2212/2228 ,  G11C11/005

摘要： In one form, a computer system includes a central processing unit, a memory controller coupled to the central processing unit and capable of accessing non-volatile random access memory (NVRAM), and an NVRAM-aware operating system. The NVRAM-aware operating system causes the central processing unit to selectively execute selected ones of a plurality of application programs, and is responsive to a predetermined operation to cause the central processing unit to execute a memory persistence procedure using the memory controller to access the NVRAM.

摘要翻译： 在一种形式中，计算机系统包括中央处理单元，耦合到中央处理单元并且能够访问非易失性随机存取存储器（NVRAM）的存储器控​​制器以及支持NVRAM的操作系统。 所述NVRAM感知操作系统使得所述中央处理单元选择性地执行多个应用程序中的选定的应用程序，并且响应于预定操作，以使所述中央处理单元执行使用所述存储器控制器访问所述NVRAM的存储器持久性过程 。