公开(公告)号：US20100169398A1

公开(公告)日：2010-07-01

申请号：US12561795

申请日：2009-09-17

申请人： MANFRED KOPP

发明人： MANFRED KOPP

IPC分类号： G06F7/487 ,  G06F5/01 ,  G06F7/485

CPC分类号： G06F7/4876 ,  G06F7/49963 ,  G06F7/5272 ,  G06F2207/3852 ,  H03M7/24

摘要： The invention pertains to a device such as a sensor, operator device, communication device, or a liquid level metering device, with a measured value input to apply a measured value. The device includes at least a first memory region to provide for an adjustment factor, and a computer, which is designed and/or controlled to multiply a first whole number by a floating-point number to obtain a product of the multiplication, while the first whole number corresponds either to the applied measured value or the provided adjustment factor; and, the floating-point number corresponds to the other measured value or to the adjustment factor. The computer has a second memory region for the storing of the floating-point number in a format of a second whole number, and the computer is designed and/or controlled to carry out a multiplication of the first whole number and the second whole number.

摘要翻译： 本发明涉及诸如传感器，操作者装置，通信装置或液位计量装置的装置，具有测量值输入以应用测量值。 该设备至少包括一个提供调整因子的第一存储器区域和一个被设计和/或控制以将第一整数乘以浮点数来获得乘法乘积的计算机，而第一个 整数对应于应用的测量值或提供的调整因子; 并且，浮点数对应于另一个测量值或调整因子。 计算机具有用于以第二整数的格式存储浮点数的第二存储器区域，并且计算机被设计和/或控制以执行第一整数和第二整数的乘法。

公开(公告)号：US5841674A

公开(公告)日：1998-11-24

申请号：US845813

申请日：1997-04-29

申请人： David L. Johannsen

发明人： David L. Johannsen

IPC分类号： G06F7/52 ,  G06F17/50

CPC分类号： G06F7/5318 ,  G06F17/5045 ,  G06F2207/3852

摘要： A circuit design tool which includes an architecture for a multiplier which is faster and more compact than known multipliers through the use of Wallace trees, the elimination of Dadda nodes along the critical paths, the placement of half-adders at an initial pat of the Wallace tree, the replacement of low-order terminating adders with ripple-carry adders, and the replacement of high-order terminating adders with carry-select adders.

摘要翻译： 一种电路设计工具，包括一个乘法器的架构，通过使用华莱士树，比已知的乘法器更快更紧凑，沿着关键路径消除了Dadda节点，在华莱士的初步拍摄中放置了半加法器 树，替换带有纹波加载器的低阶终端加法器，并用携带选择加法器替换高阶终止加法器。

公开(公告)号：US5224065A

公开(公告)日：1993-06-29

申请号：US814719

申请日：1991-12-30

申请人： Makoto Yoshida

发明人： Makoto Yoshida

IPC分类号： G06F7/501 ,  G06F7/50 ,  G06F7/503 ,  G06F7/506 ,  G06F7/575

CPC分类号： G06F7/503 ,  G06F7/575 ,  G06F2207/3852

摘要： A bit-inversion arithmetic operation unit comprises a first carry signal line for propagating a carry signal from a more significant bit position side to a less significant bit position side, and a second carry signal line for propagating a carry signal from a less significant bit position side to a more significant bit position side. A common logic circuit performs at least a portion of a carry control including a carry propagation of the first and second carry signals and a carry generation. A switching and logic circuit responds to a required arithmetic operation mode so as to control the common logic circuit and to perform the remaining portion of the carry control including the carry propagation of the first and second carry signals and the carry generation.

公开(公告)号：US4970676A

公开(公告)日：1990-11-13

申请号：US333052

申请日：1989-04-04

申请人： Russell T. Fling

发明人： Russell T. Fling

IPC分类号： G06F7/53 ,  G06F7/52 ,  G06F7/523

CPC分类号： G06F7/5272 ,  G06F2207/3852

摘要： A word serial multiplier includes a first circuit loop for loading a parallel-bit multiplier, and in response to a clock signal sequentially produces a gate signal corresponding to a sequence of bits of the multiplier sample in descending order of significance. A second circuit loop loads a multiplicand sample and in response to the clock signal successively divides the multiplicand sample by the factor two. The more significant bits, exclusive of the least significant bit, of the divided multiplicand sample are coupled to a gating circuit. The gating circuit passes the more significant bits to the input of an accumulator if the corresponding bits of the gate signal exhibit a predetermined state. After a number of cycles of the clock signal, corresponding to the number of bits m of the multiplier sample, the accumulator produces a scaled product equal to the muliplicand times the multiplier times the scale factor of 2.sup.-(m-1).

摘要翻译： 字串行乘法器包括用于加载并行比特乘法器的第一电路回路，并且响应于时钟信号按重要性的顺序顺序地产生与乘法器样本的比特序列相对应的门信号。 第二个电路环路加载被乘数的采样，响应于时钟信号，连续的将被乘数除以因子2。 分频乘法器采样的排除最低有效位的更高有效位被耦合到门控电路。 如果门信号的相应位呈现预定状态，门控电路将更高有效位传递给累加器的输入。 在对应于乘法器样本的位数m的时钟信号的多个周期之后，累加器产生等于乘数乘以倍数乘以2-（m-1）的比例因子的缩放乘积。

公开(公告)号：US4047011A

公开(公告)日：1977-09-06

申请号：US639517

申请日：1975-12-15

申请人： Walter Scott Bennett

发明人： Walter Scott Bennett

IPC分类号： G06F7/52 ,  G06F7/57

CPC分类号： G06F7/5272 ,  G06F7/535 ,  G06F7/57 ,  G06F2207/3852 ,  G06F2207/5353 ,  G06F2207/5356

摘要： Three modular arrays structured from a common module are connected together a first way to form a binary quotient by successive approximations, or a second way to form a binary product. Any one of the three modular arrays may be used to add or subtract two binary numbers. To divide, one array is utilized to generate a shift and add sequence that represents the reciprocal of the divisor, most significant bit first. As this add and shift sequence is being formed, it is, at the same time, being utilized to manipulate the dividend, thereby forming the quotient, most significant bit first. In effect, the dividend is being multiplied by the reciprocal of the divisor so as to form a product of the dividend and reciprocal of the divisor, most significant bit first. This product is actually the quotient of the dividend and divisor. The binary product of two numbers is formed, most significant bit first, by manipulating the multiplicand according to an add and shift sequence determined by use of the multiplier.

摘要翻译： 由公共模块构成的三个模块化阵列通过逐次逼近形成二进制商的第一种方式连接在一起，或者形成二进制产品的第二种方法。 三个模块阵列中的任何一个可用于加或减两个二进制数。 为了划分，使用一个数组来产生代表除数倒数的移位和加法序列，最高有效位。 由于正在形成这个加法和移位序列，同时利用它来操纵分红，从而形成商，最重要的是位。 实际上，红利乘以除数的倒数，从而形成除数的乘数和倒数的乘积，最重要的是位。 该产品实际上是股息和除数的商。 通过根据通过使用乘法器确定的加法和移位序列来操纵被乘数，形成两个数字的二进制积，最高有效位。

公开(公告)号：US3535498A

公开(公告)日：1970-10-20

申请号：US3535498D

申请日：1967-05-02

申请人： DETREX CHEM IND

发明人： SMITH LOUIS G JR

IPC分类号： G06F7/52 ,  G06F7/552 ,  G06F7/57 ,  H03M7/12 ,  G06F7/38 ,  G06F5/02 ,  H03K5/00

CPC分类号： G06F7/5306 ,  G06F7/535 ,  G06F7/552 ,  G06F7/5525 ,  G06F7/57 ,  G06F2207/3852 ,  G06F2207/3868 ,  G06F2207/5352 ,  G06F2207/5523 ,  H03M7/12

公开(公告)号：US2404697A

公开(公告)日：1946-07-23

申请号：US43574642

申请日：1942-03-21

申请人： NCR CO

发明人： DESCH JOSEPH R ,  MUMMA ROBERT E

IPC分类号： G06F7/52

CPC分类号： G06F7/5272 ,  G06F2207/3852

公开(公告)号：US08443019B2

公开(公告)日：2013-05-14

申请号：US12561795

申请日：2009-09-17

申请人： Manfred Kopp

发明人： Manfred Kopp

IPC分类号： G06F7/00 ,  G06F15/00

CPC分类号： G06F7/4876 ,  G06F7/49963 ,  G06F7/5272 ,  G06F2207/3852 ,  H03M7/24

摘要： The invention pertains to a device such as a sensor, operator device, communication device, or a liquid level metering device, with a measured value input to apply a measured value. The device includes at least a first memory region to provide for an adjustment factor, and a computer, which is designed and/or controlled to multiply a first whole number by a floating-point number to obtain a product of the multiplication, while the first whole number corresponds either to the applied measured value or the provided adjustment factor; and, the floating-point number corresponds to the other measured value or to the adjustment factor. The computer has a second memory region for the storing of the floating-point number in a format of a second whole number, and the computer is designed and/or controlled to carry out a multiplication of the first whole number and the second whole number.

摘要翻译： 本发明涉及诸如传感器，操作者装置，通信装置或液位计量装置的装置，具有测量值输入以应用测量值。 该设备至少包括一个提供调整因子的第一存储器区域和一个被设计和/或控制以将第一整数乘以浮点数来获得乘法乘积的计算机，而第一个 整数对应于应用的测量值或提供的调整因子; 并且，浮点数对应于另一个测量值或调整因子。 计算机具有用于以第二整数的格式存储浮点数的第二存储器区域，并且计算机被设计和/或控制以执行第一整数和第二整数的乘法。

公开(公告)号：US5910898A

公开(公告)日：1999-06-08

申请号：US572520

申请日：1995-12-14

申请人： David L. Johannsen

发明人： David L. Johannsen

IPC分类号： G06F7/52 ,  G06F17/50

CPC分类号： G06F7/5318 ,  G06F17/5045 ,  G06F2207/3852

摘要： A circuit design tool which includes (1) separating structural and functional aspects of components, so as to specify the desired functional behaviour of the component, leaving the actual gate-level design of the component to the design tool; (2) translating a model of the desired logical behaviour of a circuit into a regularized set of functional components to achieve that desired behaviour; (3) verifying structural equivalence between pairs of components; (4) a method for bit-reversing the signal flow in a component; (5) a method for performing arithmetic operations backwards from a natural order; (6) an architecture for a multiplier which is faster and more compact than known multipliers; and (7) a method of translating a logic equation into a netlist of connected logic gates.

摘要翻译： 一种电路设计工具，其包括（1）分离组件的结构和功能方面，以便指定组件的期望功能行为，将组件的实际门级设计留给设计工具; （2）将电路的期望逻辑行为的模型转换成正规化的一组功能组件以实现所需的行为; （3）验证组件对之间的结构等效性; （4）一种用于对组件中的信号流进行位反转的方法; （5）从自然顺序向后执行算术运算的方法; （6）乘法器的架构，比已知乘法器更快，更紧凑; 和（7）将逻辑方程转换成连接的逻辑门的网表的方法。

公开(公告)号：US5524090A

公开(公告)日：1996-06-04

申请号：US512620

申请日：1995-08-08

申请人： Keiichi Iwamura

发明人： Keiichi Iwamura

IPC分类号： G06F7/52 ,  G06F7/72

CPC分类号： G06F7/5324 ,  G06F7/533 ,  G06F7/722 ,  G06F2207/3852 ,  G06F2207/3892 ,  G06F7/723

摘要： A multiplier apparatus designed to multiply integers of many figures with a small circuit scale in such a manner that an input value is partitioned and multiplication is performed by taking account of carries. With respect to partitioned input values, partial multiplications are repeatedly performed in parallel with each other, and results of the partial multiplications are added by a plurality of adders. A carry occurring at each adder is added in the same adder or in an upper adder in the next cycle of addition. A circuit for this operation may be formed as a systolic array of identical processing elements to perform the operation in a pipe line processing manner.

摘要翻译： 一种乘法器装置，被设计为以一种小的电路规模乘以多个数字的整数，使得输入值被分割并且通过考虑运算来执行乘法。 对于分割输入值，部分乘法相互并行重复执行，部分乘法的结果由多个加法器相加。 在下一个加法循环中，在相同的加法器或上加法器中，加法出现在每个加法器。 用于该操作的电路可以形成为相同处理元件的收缩阵列，以管线处理方式执行操作。