公开(公告)号：US20160034256A1

公开(公告)日：2016-02-04

申请号：US14449850

申请日：2014-08-01

申请人： Imagination Technologies, Limited

发明人： Leonard Rarick

IPC分类号： G06F7/535

CPC分类号： G06F7/535 ,  G06F2207/5353

摘要： Embodiments disclosed pertain to apparatuses, systems, and methods for fast integer division. Disclosed embodiments pertain to an integer divide circuit to divide a dividend by a divisor and produce multiple quotient bits per iteration. In some embodiments, the fast integer divider may include a partial remainder register initialized with the dividend. Further, the fast integer divider circuit may include a plurality of adders, where each adder subtracts a multiple of the divisor from the current value in the partial remainder register. A logic block coupled to each of the adders, determines multiple quotient bits at each iteration based on the subtraction results.

摘要翻译： 所公开的实施例涉及用于快速整数除法的装置，系统和方法。 公开的实施例涉及一个整数除法电路，以将除数除以除数，并产生每次迭代的多个商位。 在一些实施例中，快速整数除法器可以包括用分红初始化的部分余数寄存器。 此外，快速整数分频器电路可以包括多个加法器，其中每个加法器从部分余数寄存器中的当前值中减去除数的倍数。 耦合到每个加法器的逻辑块基于减法结果在每次迭代确定多个商位。

公开(公告)号：US20140059106A1

公开(公告)日：2014-02-27

申请号：US13935175

申请日：2013-07-03

申请人： Fujitsu Limited

发明人： Kensuke Shinomiya ,  Kenichi Kitamura

IPC分类号： G06F7/52

CPC分类号： G06F7/52 ,  G06F7/535 ,  G06F2207/5353

摘要： An arithmetic circuit for performing division based on restoring division includes an intermediate remainder register configured to store an intermediate remainder, a quotient prediction circuit configured to perform, based on information about two most significant digits of the intermediate remainder and a most significant digit of a divisor, quotient prediction having lower precision than a highest precision obtainable from the information, thereby generating a prediction result, a fixed-value multiplication circuit configured to output one or more N-th (N: integer) multiples of the divisor selected in response to the prediction result, one or more subtracters configured to subtract, from the intermediate remainder, the one or more N-th multiples of the divisor output from the fixed-value multiplication circuit, and a partial quotient calculating circuit configured to obtain a partial quotient in response to one or more carry-out bits of one or more subtractions performed by the one or more subtracters.

摘要翻译： 用于基于恢复分割执行分割的算术电路包括被配置为存储中间余数的中间余数寄存器，商预测电路被配置为基于关于中间余数的两个最高有效数字和除数的最高有效数字的信息来执行 具有比从信息可获得的最高精度更低的精度的商预测，从而产生预测结果;固定值乘法电路，被配置为输出响应于所述信息所选择的除数的一个或多个第N（N：整数）个倍数 预测结果，一个或多个减法器被配置为从中间余数中减去从固定值乘法电路输出的除数的一个或多个N倍，以及部分商计算电路，被配置为获得响应中的部分商 到由一个或多个执行的一个或多个减法的一个或多个进位位 或更多的减法器。

公开(公告)号：US20120089658A1

公开(公告)日：2012-04-12

申请号：US13377650

申请日：2010-06-10

申请人： Jung Uk Woo ,  In Tae Kang ,  Yun Ju Kwon ,  Dong Min Kim

发明人： Jung Uk Woo ,  In Tae Kang ,  Yun Ju Kwon ,  Dong Min Kim

IPC分类号： G06F7/491 ,  G06F7/52 ,  G06F7/50

CPC分类号： G06F7/72 ,  G06F7/535 ,  G06F2207/5353

摘要： The present invention provides a modulo operation method. The modulo operation method, in a case where the square of a divisor N is greater than or equal to a dividend C, includes: determining the number of computation stages n satisfying 2n

摘要翻译： 本发明提供一种模运算方法。 在除数N的平方大于或等于除数C的情况下，模运算方法包括：确定满足2n

公开(公告)号：US07487197B2

公开(公告)日：2009-02-03

申请号：US11755128

申请日：2007-05-30

申请人： David J Clark ,  Michael F Cowlishaw

发明人： David J Clark ,  Michael F Cowlishaw

IPC分类号： G06F7/52

CPC分类号： G06F7/535 ,  G06F2207/5353

摘要： A data processing apparatus uses numeric processing. A corrective mechanism enables a method for performing accurate integer divisions to be derived from an approximate division method which does not, of itself, always produce an accurate result but for which the range of errors is known. By applying the corrective mechanism to a suitable approximate division method, a numeric processing mechanism performs the integer division operation efficiently. An approximate division method that uses rapid operations for fast integer division, and thus has a small possible range of errors, is used to enable the correction method to be completed rapidly.

摘要翻译： 数据处理装置使用数字处理。 校正机制使得能够从近似分割方法导出精确的整数除法的方法，该近似除法本身不总是产生准确的结果，而是误差范围是已知的。 通过将校正机制应用于合适的近似分割方法，数字处理机构有效地执行整数除法运算。 一种使用快速运算进行快速整数除法，因此具有较小可能误差范围的近似除法，用于使校正方法快速完成。

公开(公告)号：US07277908B2

公开(公告)日：2007-10-02

申请号：US10319270

申请日：2002-12-13

申请人： David J Clark ,  Michael F Cowlishaw

发明人： David J Clark ,  Michael F Cowlishaw

IPC分类号： G06F7/52

CPC分类号： G06F7/535 ,  G06F2207/5353

摘要： Provided are methods, computer programs and data processing apparatus using numeric processing. Firstly, a corrective mechanism enables a method for performing accurate integer divisions to be derived from an approximate division method which does not, of itself, always produce an accurate result but for which the range of errors is known. By applying the corrective mechanism to a suitable approximate division method, a numeric processor or software-implemented numeric processing mechanism implementing the invention can perform the integer division operation efficiently. Secondly, an approximate division method which uses only rapid operations for fast integer division, and which has only a small possible range of errors, is used to enable the correction method to be completed rapidly. This addresses problems encountered when attempting to apply known methods to the task of performing integer division by large divisors or in a limited-size numeric register, and can provide efficiency improvements for a wide range of data processing systems and applications of those systems.

摘要翻译： 提供了使用数字处理的方法，计算机程序和数据处理装置。 首先，校正机制使得能够从近似分割方法导出精确整数分割的方法，该近似除法本身不总是产生准确的结果，而是误差范围是已知的。 通过将校正机制应用于合适的近似分割方法，实现本发明的数字处理器或软件实现的数字处理机构可以有效地执行整数除法运算。 其次，使用仅使用快速整数除法的快速操作并且仅具有小的可能误差范围的近似除法来使得校正方法能够快速完成。 这解决了尝试将已知方法应用于通过大型除数或大小数字寄存器执行整数除法的任务时遇到的问题，并且可以为广泛的数据处理系统和这些系统的应用提供效率改进。

公开(公告)号：US07117237B2

公开(公告)日：2006-10-03

申请号：US10375995

申请日：2003-02-28

申请人： Kazuhiko Amano ,  Tsugio Nakamura ,  Hiroshi Kasahara ,  Tatsuya Shimoda

发明人： Kazuhiko Amano ,  Tsugio Nakamura ,  Hiroshi Kasahara ,  Tatsuya Shimoda

IPC分类号： G06F7/38

CPC分类号： G06F7/57 ,  G06F7/535 ,  G06F7/723 ,  G06F21/72 ,  G06F2207/3816 ,  G06F2207/5353 ,  G06F2221/2149

摘要： An information processing system that is configured in such a manner that computational processing is performed on input data in accordance with a processing sequence, for outputting data, comprises: a plurality of arithmetic units (7-1 to 7-x), each computing at an arithmetic precision 2m bits (where m is a natural number) based on the processing sequence; and a plurality of cascade connection terminals for cascading these arithmetic units each other. When the maximum arithmetic precision that is required during computational processing is 2n bits (where n is a natural number and is fixed), x numbers of (where x is a natural number) the arithmetic units are cascaded in a manner such that the inequality x≧2n/2m is satisfied. When an arithmetic precision of 2n1 bits (where n1≦n, and n1 is variable) is necessary during computational processing, x1 numbers of the arithmetic units are cascaded in a manner such that the inequality x1≧2n1/2m (where x1 is a natural number and is variable) is satisfied. This makes it possible to easily implement an information processing system for performing computations to any desired precision in a hardware manner, and also makes it possible to support a simple hardware-based method of expanding the arithmetic precision.

摘要翻译： 一种信息处理系统，其被配置为使得根据用于输出数据的处理序列对输入数据进行计算处理的方式包括：多个运算单元（7-1至7-x），每个运算单元 基于处理顺序的算术精度2 位（其中m是自然数） 以及用于将这些算术单元彼此级联的多个级联连接端子。 当计算处理期间所需的最大算术精度为2个比特（其中n是自然数并且是固定的）时，算术单元级联的（其中x是自然数）的x个数 以满足不等式x> = 2 / 2 的方式。 当在计算处理期间需要2×n1位的运算精度（其中n1 <= n和n1是可变的）时，运算单元的x1个数以这样的方式级联，使得不等式x1> = 2＆lt; n1＆lt; / 2＆gt;（其中x1是自然数并且是可变的）。 这使得可以容易地实现用于以硬件方式执行任何期望精度的计算的信息处理系统，并且还可以支持扩展算术精度的简单的基于硬件的方法。

公开(公告)号：US20030220958A1

公开(公告)日：2003-11-27

申请号：US10407148

申请日：2003-04-03

申请人： STMicroelectronics Asia Pacific PTE Limited ,  National University of Singapore

发明人： Christopher Anthony Aldridge ,  Wee Tiong Tan ,  Chia Kwang Kang

IPC分类号： G06F007/52

CPC分类号： G06F7/535 ,  G06F2207/5353

摘要： A method of dividing, in a micro computer unit (MCU), a first binary number (N), having a first number of significant bits, by a second binary number (D), having a second number of significant bits, produces an integer result (Y). The method includes: determining the difference (K) between the first and second numbers of significant bits; aligning the most significant bits (MSBs) of N and D by shifting the bits of D, by K bit positions, such that its MSB occupies the same relative bit position as the MSB of N; repeating K times: multiplying Y by 2; dividing D by 2; and, if N is greater than or equal to D: increasing Y by 1; setting N equal to NnullD.

摘要翻译： 一种在微计算机单元（MCU）中划分具有第二数目有效位的具有第二数目的有效位的第二二进制数（D）的具有第二数目的有效位的第一二进制数（N）产生一个整数 结果（Y）。 该方法包括：确定第一和第二有效位数之间的差（K）; 通过将D的位移位K位位置来对齐N和D的最高有效位（MSB），使得其MSB占据与N的MSB相同的相对位位置; 重复K次：将Y乘以2; 将D除以2; 并且如果N大于或等于D：将Y增加1; 设置N等于N-D。

公开(公告)号：US06625633B1

公开(公告)日：2003-09-23

申请号：US09585894

申请日：2000-06-01

申请人： Koji Hirairi

发明人： Koji Hirairi

IPC分类号： G06F752

CPC分类号： G06F7/535 ,  G06F2207/5353

摘要： A high radix divider capable of reducing the size of the circuit of a quotient/remainder judgement unit in a radix 2k restoring division divider for finding a quotient k number of bits at a time, comparing multiples B, 2B, and 3B of a divisor B with a remainder R in parallel in two-input comparators and a three-input comparator and performing radix 4 division by finding a quotient 2 bits at a time. At this time, using a three-input comparator 313 in the comparison of 3B=(B+2B)≦R to realize comparison without the addition (B+2B), also, finding a new remainder Re in a three-input adder/subtractor for the simultaneous complex addition/subtraction R−(x+y) by a single ripple carry.

摘要翻译： 一个高基数分频器，其能够减小基数2k恢复分频器中的商/余数判断单元的电路的大小，以便一次找到商k个位数，将B，2B和3B的倍数比较 具有两个输入比较器并联的余数R的除数B和三输入比较器，并且一次通过寻找商2位执行小数4除法。 此时，在比较3B =（B + 2B）<= R的情况下使用三输入比较器313来实现比较而没有加法（B + 2B），同样，在三输入加法器中找到新的余数Re /减法器，用于通过单个纹波进位同时复加数/减法R-（x + y）。

公开(公告)号：US5805489A

公开(公告)日：1998-09-08

申请号：US646178

申请日：1996-05-07

申请人： John Susantha Fernando

发明人： John Susantha Fernando

IPC分类号： G06F7/537 ,  G06F5/01 ,  G06F7/52 ,  G06F7/535

CPC分类号： G06F7/535 ,  G06F5/01 ,  G06F2207/5353

摘要： The present invention is a variable-delay division (VDD) scheme implementable in hardware to execute signed and unsigned integer division and remainder operations in digital processor. The VDD scheme advantageously uses hardware utilized for multiplication to implement a 2-bits/cycle alignment step to iteratively align the divisor with the dividend. This speeds up the alignment phase of integer division. Quotient bits are produced at the rate of 1-bit/cycle using the well-known restoring scheme. For 32-bit 2's complement operands, the scheme has a delay less than a fixed-delay scheme for most operands.

摘要翻译： 本发明是一种在硬件中实现的可变延迟分频（VDD）方案，用于在数字处理器中执行有符号和无符号整数除法和余数运算。 VDD方案有利地使用用于乘法的硬件来实现2比特/周期对准步骤，以将除数与被除数重复对齐。 这加快了整数除法的对齐阶段。 使用众所周知的恢复方案以1位/周期的速率产生商数位。 对于32位2的补码操作数，该方案的延迟小于大多数操作数的固定延迟方案。

公开(公告)号：US5485414A

公开(公告)日：1996-01-16

申请号：US214315

申请日：1994-03-17

申请人： Mitsuyoshi Yao ,  Kohichi Ueda

发明人： Mitsuyoshi Yao ,  Kohichi Ueda

IPC分类号： G06F7/52 ,  G06F7/535 ,  G06F7/72

CPC分类号： G06F7/535 ,  G06F7/72 ,  G06F2207/5353

摘要： A divider circuit which calculates an integral quotient of an integral divisor and an integral dividend. A first multiplication unit calculates products of the integral divisor and all n-bit pattern values of an n-bit pattern, where n is a predetermined number and the n-bit pattern values respectively correspond to the calculated products. A calculation unit sets the integral dividend as an initial value of an operational integer, specifies a product among the products calculated by the first multiplication unit of which the subordinate n-bit value is equal to the subordinate n-bit value of the operational integer, and calculates a difference of the operational integer and the specified product. When the difference calculated by the calculation unit is not zero, an activation unit sets a new operational integer by canceling the subordinate n bits of the difference and causes the calculation unit to set the integral dividend, specify a product and calculate a difference based on the new operational integer. An output unit successively takes n-bit pattern values respectively corresponding to products specified by the calculation unit, and outputs these n-bit pattern values as the quotient when the difference calculated by the calculation unit is zero.

摘要翻译： 一个分频电路，用于计算积分因子和积分除数的积分商。 第一乘法单元计算n位模式的积分因子和所有n位模式值的乘积，其中n是预定数，并且n位模式值分别对应于所计算的乘积。 计算单元将积分分红设置为运算整数的初始值，指定由下级n位值等于运算整数的从属n位值的第一乘法单元计算出的乘积之间的乘积， 并计算操作整数和指定乘积的差。 当由计算单元计算出的差值不为零时，激活单元通过取消差值的下位n位来设置新的运算整数，并使计算单元设置积分分红，指定乘积并基于 新的运算整数。 输出单元连续地取得由计算单元指定的产品分别对应的n位模式值，并且当计算单元计算的差为零时，将这些n位模式值作为商进行输出。