Abstract:
A station address displayed in a display field coincides with a station address of a PLC (Programmable Logic Controller) to which a personal computer is connected. Further, bit addresses of respective output variables are displayed in a display field. For example, a corresponding bit corresponding to a check box whose address of the output variable is 00L1E and whose station address of the destination PLC is 2 is an output schedule definition bit in an output schedule definition frame stored in a first storage. Therefore, a value of the output schedule definition bit is defined as 0 (: output is not scheduled). When an OK button is clicked, respective output schedule definition frames defined correctly are transferred to a PLC and then are stored in the first storage respectively.
Abstract:
A parallel process controller capable of expandable, parallel operating multi-function control of processes without degradation of performance. The process controller comprises up to N (where N is a positive integer) programmable command memory modules, and also comprises data memory modules, an input/output system, a high speed data bus (N-bus) and a general timing and control unit. Each command memory module performs the functional equivalent of a central processing unit with storage of instruction lines designatable by a user via a programming panel. Each command memory module operates autonomously, without regard to the other command memory modules and cyclically solves each of the user instruction lines in a short, fixed length of time. Each data memory module supplements data storage in the command memory modules. The N-bus is a high speed data bus that cyclically interconnects for a fixed length of time each command memory module during one of N control signals generated by the general timing and control unit, to any of the data memory modules and to the input/output system. During this length of time, the selected command memory module may address, read, or write in any location in any data memory module. An interconnectable programming panel may monitor, program, or control line status indicators for any instruction line within any command module or any line within any data memory module. The programming panel communicates with the controller via a dedicated channel of the input/output system.
Abstract:
An IO-Link master includes: an IO-Link communication port that communicates with an IO-Link device according to a predetermined communication protocol; a digital input port that receives a first signal value output from the IO-Link device; and a determiner that determines whether abnormality is generated in a digital input line connecting the digital input port to the IO-Link device based on a second signal value received with the IO-Link communication port and the first signal value.
Abstract:
A communication circuit sends asynchronous digital signals in parallel to an external device. A first parity circuit in the communication circuit computes a first bit which indicates the parity of the control signals. This first bit is sent to the external device. When the digital signals and the parity bit are received by the external device, a first control signal is produced when each of the received digital signals has the same logic level for a defined period of time. A second parity circuit produces a second control signal when a parity error is found in the received digital signals. An error signal is generated in response to the presence of both the first and second control signals.
Abstract:
The PLC communication system associated with the invention is characterized in that the system comprises a programmable logic controller (PLC), a plurality of processing devices, at least three communication processing nodes provided at the PLC and at the plurality of processing devices respectively to establish communication of the PLC and each of the processing devices and an interconnecting device and a plurality of communication lines for connecting the communication processing nodes with one another to establish data communication among the communication processing nodes. The PLC detects a state of communication failure and a display device displays an abnormal portion in a communication route based on the number of occurrences of the state of communication failure in respective interconnecting device and plurality of communication lines.
Abstract:
A programmable controller includes four remotely located input/output interface racks which are connected by cables to an I/O scanner circuit which is centrally located with the controller processor and memory. Input and output data is serially transmitted between the I/O scanner circuit and the interface racks, and fault processors are located in both the I/O scanner circuit and the interface racks to monitor the operation. The fault processors include fault tolerant detector circuits which ignore erroneous transmissions caused by industrial noise, but which initiate a shutdown process when malfunctions occur. The shutdown process is controlled by a programmable disabling circuit which is responsive to program instructions stored in the controller memory to allow independent, quasi-independent, or dependent operation of the machines connected to each of the four interface racks.
Abstract:
A telecommunications system for a programmable logic controller (PLC) includes: a master module comprising a transmitter and a receiver; one or more slave modules configured to receive signals transmitted from the transmitter and transmit signals to the receiver in response to the transmitted signals; a signal conversion module configured to convert the signals transmitted between the master module and the slave modules into digital signals; a control module configured to control the signal conversion module and to determine whether there is an error in the signals transmitted between the master module and the slave modules based on the digital signals; a display module configured to display a result of the determination by the control module.
Abstract:
The PLC communication system associated with the invention is characterized in that the system comprises a programmable logic controller (PLC), a plurality of processing devices, at least three communication processing nodes provided at the PLC and at the plurality of processing devices respectively to establish communication of the PLC and each of the processing devices and an interconnecting device and a plurality of communication lines for connecting the communication processing nodes with one another to establish data communication among the communication processing nodes. The PLC detects a state of communication failure and a display device displays an abnormal portion in a communication route based on the number of occurrences of the state of communication failure in respective interconnecting device and plurality of communication lines.
Abstract:
A station address displayed in a display field W5 coincides with a station address of the PLC to which this personal computer is connected. Further, bit addresses of respective output variables are displayed in a display field W1. For example, a corresponding bit corresponding to a check box whose address of the output variable is 00L1E and whose station address of the destination PLC is 2 is an output schedule definition bit Rb1E in an output schedule definition frame RF02 stored in a first storing unit TBL1. Therefore, a value of the output schedule definition bit Rb0E is defined as 0 (output is not scheduled). When an OK button W4 is clicked, respective output schedule definition frames are transferred to a PLC 10 and then are stored in the first storing unit TBL1 respectively.
Abstract:
A network consists of a programmable controller coupled to several sensors by an interface circuit. A common communication protocol is used to exchange messages containing commands and data between the devices coupled to the network. A protocol message packet has a header with fields for a task command, sensor identification, device status information and error codes. The header contains the same fields whether the message packet is for the interface circuit or one of the sensors connected to it. The headers for message packets going to and from the programmable controller and the interface circuit also have the same fields although the contents of the fields may vary depending upon the direction of the message packet. The message packet may also contain several data blocks each specifying a separate operation for the sensor to perform.