Abstract:
Provided is a remote terminal device having an industrial versa module eurocard bus (VMEbus) structure and including a main module that receives control logic information of a field device from an input/output module, and a programmable logic controller (PLC) function module that receives the control logic information from the main module, performs a logic corresponding to the control logic information, and outputs a result of the performed logic. The PLC function module includes a dual port RAM including a plurality of memory areas, and a PLC chip that reads the control logic information written on one of the plurality of memory areas, performs the logic corresponding to the read control logic information, and outputs the result of the performed logic to another one of the plurality of memory areas.
Abstract:
An industrial control system employs a primary and secondary controller each having a processor and at least one I/O data table. Updating of the secondary processor's I/O data table is performed prior to the same data being transmitted to the controlled process. This eliminates possible retrogressive control at the time of switch-over of control from the primary industrial controller to the secondary industrial controller. Additional I/O data tables may be provided in each of the primary and secondary industrial controllers. In the case of the secondary industrial controller, this duplicate I/O data table temporarily holds data until the transmission is complete preventing the partial update of the working I/O data table of the secondary industrial controller. The duplicate I/O data table in the primary industrial controller allows simultaneous outputting of the I/O data transmitted to the controlled process without corruption while the user program of the primary industrial controller resumes execution.
Abstract:
An industrial controller has an I/O scanner that may scan I/O modules at differing rates depending on the intrinsic bandwidth of the controlled process variable. The user defines an update rate for each I/O module reflecting the bandwidth of its associated variable. The scanner continuously updates a table of I/O events for each I/O module or I/O rack listing permissive and mandatory I/O execution times associated with each event. Using this event table, the I/O scanner determines the next I/O module to be serviced. If the event cannot be serviced on schedule, indication of an event slip is reported to the controller.
Abstract:
A high-speed press control system including a control processor and an associated scan processor for executing a press algorithm providing timed interrupts and consisting of identical programmable sub-algorithms to control output and input registers. The high-speed press control system has the capability of monitoring and reacting to press position every 2.5 ms.
Abstract:
A programmable logic controller includes a plurality of input interfaces and a plurality of output interfaces for connection to industrial equipment such as automatic assembly equipment, textile machinery, materials handling equipment, and chemical processes. The input and output circuits can be randomly addressed as to their state through an eight bit bus, which connects in parallel with up to 16 groups of eight input and/output circuits. The controller includes groups of timers which are each manually adjustable as to the timing operation and which are sequentially addressed each time a timing function is called for by the program. The timers are designed to be cascaded in groups to virtually any number of timers. The controller includes a scratch pad memory, half of which retains memory upon power failure and half of which does not. The control of the controller by the operator is made more nearly foolproof by interlocking the operations of control switches. Three programming instructions are available which are conditional upon the data in the accumulator of the controller.
Abstract:
A programmable controller sequentially executes a control program at a basic "scan rate" determined by the length of the program and the speed at which the controller processor executes the instructions therein. At the completion of each scan through the control program an I/O scan is performed which inputs the status of all sensing devices to the controller image table and outputs status data from the image table to operating devices. The present invention enables the status of selected sensing devices to be inputted and acted upon at any point during the scan through the control program and it enables the output of the processor logic unit to be coupled to a selected operating device at any point. The rate at which selected I/O devices can be scanned by the controller is thus programmable and may be much higher than the basic scan rate of the controller.
Abstract:
A stored-logic real time monitoring and control system which includes a first storage device for sequentially storing the switching logic descriptions of a desired combinational sequential or the like logic function to be performed and a second storage device for storing the present input status to the switching logic descriptions. Individual hardware versions of the desired switching logic descriptions are provided and selectively allowed to repetitively operate upon the monitored input signals in accordance with the stored switching logic descriptions in such a fashion as to allow the desired real time monitoring and control.
Abstract:
The invention relates to a method for operating a data processing device (SPS) as a memory-programmable control unit. In order to attain a rapid processing of entry and/or outlet data with low memory consumption, the process includes the following steps: Reading in entry data (E0 . . . En.n) applying on entry components (E0 . . . En), Storing entry data in a memory (DS) as process image (PAE) of entries such that a bit allocated to each entry (E0.0 . . . En.n) of a memory position (SZ) is set to zero or one, Building up a memory region according to the type of a stack (BIT, ST, BY ST, WST, DWST, QWST) with entry data (E0.0 . . . En.n) required with a subsequent program processing, Loading the entry data (E0.0 . . . En.n) filed in the stack (BITST, BYST, BST, DWST, QWST) into the processor register, Generating outlet data (A0.0 . . . An.n) by servicing a program code with the entry data deposited in the processor register (DX) such that the processor register (DX) contains corresponding outlet data following the processing, Storage of the outlet data contained in the processor register (DX) into memory (DS) as a process image (PAA) of the outlets such that a bit of each memory position allocated to each outlet is set to zero or one, and Transferring the outlet data (A0.0 . . . An.n) stored in memory to an outlet component (A0 . . . An).
Abstract:
A system and method for controlling operation of a plurality of elements in an automated process, such as a production process, and indicating error conditions as they occur. Each unique set of input and output conditions of the various system elements defines a unique logic state or zone. Thus, there are defined a multiplicity of valid system logic states or zones, each having a unique input/output image. A predetermined sequence of zones, productive zones representing designed machine operations, is stored in a zone table. All zones not explicitly defined in the zone table are automatically treated as error zones. A zone engine automatically cycles to observe any change in input/output image. Any change in inputs from the various system elements automatically transfer action to the unique zone associated with such inputs, resulting in corresponding changes in control outputs to the system elements and/or display an error message as appropriate.
Abstract:
An input/output device monitors the transmission of information between a processor of a programmable controller and sensors and actuators of a process to be controlled. This device includes electronic circuits adapted for calculating the parities of the digital words which pass therethrough, these parities being compared with corresponding parities calculated by the processor which thereafter invalidates the words having two different parities.