公开(公告)号：US20090177540A1

公开(公告)日：2009-07-09

申请号：US12134904

申请日：2008-06-06

Applicant: Jesse T. Quatse

Inventor： Jesse T. Quatse

IPC: G06Q30/00 ,  G06Q90/00

CPC classification number: G06Q30/02 ,  G06Q30/0225

Abstract: A system for distributing limited numbers of promotional offers targeted to individual customers based on the customers' individual probabilities of accepting the offers is disclosed. Each customer can receive a limited number of offers estimated to be most likely to be acceptable by the customer. Customer-Based targeting analyzes each customer's past purchasing behavior relative to a master list of promotional offers made available to all customers and selects a number of promotional offers most likely to be preferred by each customer. Various techniques, such as empirical Bayes techniques and sparse data handling techniques, are disclosed for providing an offer acceptance probability profile tailored for individual customers. Product groupings and market segments are taken into account. Various marketing strategies are incorporated into the system. An individual can override a system computation and manually set the relative offer acceptance probabilities for an individual user or class of users using a graphical technique.

Abstract translation: 披露了根据客户接受要约的个人概率，分发针对个人客户的有限数量的促销优惠的系统。 每个客户可以收到估计最有可能被客户接受的有限数量的优惠。 基于客户的定位分析每个客户过去的采购行为相对于所有客户提供的促销优惠的主列表，并选择最有可能被每个客户优先选择的一些促销优惠。 公开了各种技术，例如经验贝叶斯技术和稀疏数据处理技术，以提供为个人客户定制的报价接受概率概况。 产品分组和市场细分被考虑在内。 各种营销策略纳入系统。 个人可以覆盖系统计算，并使用图形技术手动设置单个用户或一类用户的相对报价接受概率。

公开(公告)号：US4774656A

公开(公告)日：1988-09-27

申请号：US704250

申请日：1985-02-01

Applicant: Jesse T. Quatse ,  Lionel Heitz ,  Jacky Pergent ,  Olivier Penot

Inventor： Jesse T. Quatse ,  Lionel Heitz ,  Jacky Pergent ,  Olivier Penot

IPC: G05B19/02 ,  G05B19/048 ,  G05B19/05 ,  G05B23/02 ,  G06F9/02

CPC classification number: G05B19/054 ,  G05B2219/1125 ,  G05B2219/1127 ,  G05B2219/1181 ,  G05B2219/1188 ,  G05B2219/14089 ,  G05B2219/14144

Abstract: An input/output device is used for a programmable controller having on input/output cards a plurality of electronic channels forming the logic interfaces between the connection bus with the central unit and the sensors or the actuators connected to the controllers; this device further uses electronic circuits for monitoring the good transmission of input/output signals by the adaptation interfaces providing for the galvanic isolation of the bus with respect to the sensors and actuators of the controlled automatism.

Abstract translation: PCT No.PCT / FR84 / 00142 Sec。 371日期1985年2月1日 102（e）1985年2月1日PCT申请日1984年6月1日PCT公布。 出版物WO84 / 04977 日期为1984年12月20日。输入/输出装置用于具有输入/输出卡的可编程控制器，多个电子通道形成连接总线与中央单元之间的逻辑接口，以及传感器或连接到 控制器 该装置还使用电子电路来监测输入/输出信号的良好传输，该自适应接口提供总线相对于受控自动化的传感器和致动器的电隔离。

公开(公告)号：US4716541A

公开(公告)日：1987-12-29

申请号：US637772

申请日：1984-08-02

Applicant: Jesse T. Quatse

Inventor： Jesse T. Quatse

IPC: F02B75/02 ,  G05B19/05 ,  G06F9/305 ,  G06F9/38 ,  G06F9/22 ,  G05B19/18 ,  G06F9/00

CPC classification number: G06F9/30029 ,  G05B19/052 ,  G06F9/3879 ,  F02B2075/027

Abstract: A very fast and efficient Boolean processor ("BP") (20) capable of compiling a full range of diagrams or expressions in ladder, logigram, and Boolean with a small but powerful instruction set. The BP includes an instruction decoder (34), combinatoric logic (35), a T-register (42) which holds the temporary results of a sequential AND operation, an N-register (43) which holds the initial Boolean value of T, a Binary Accumulator Memory ("BAM") (40) which is used as a scratchpad for a program which evaluates a ladder or logigram diagram or a Boolean expression, a source address ("S") in BAM (40) from which an initial operand is taken, a destination address ("D") in BAM (40) in which the result of an operation is stored, and a destination address register ("DAR") (45) in which the destination address is stored. The instruction set includes a subset of input instructions and a subset of structure instructions. The operand (I) of an input instruction is an address in IOIM (25). The operands (S,D) of a structure instruction are source and destination addresses in BAM (40). Each input instruction reads the value of a bit from IOIM and has the effect of logically combining this bit value with the value held in the T-register and possibly with the destination bit in BAM. The structure instructions cause operation on the pair of addresses S and D, and either describe the structure of the diagram to be compiled or permit the performance of logical functions between nodes in the diagram.

Abstract translation: 一种非常快速高效的布尔处理器（“BP”）（20），能够使用一个小而强大的指令集来编译梯形图，逻辑图和布尔值的全范围图形或表达式。 BP包括一个指令解码器（34），组合逻辑（35），一个保持连续和运算的临时结果的T寄存器（42），保持初始布尔值T的N寄存器（43） 二进制累加器存储器（“BAM”）（40），用作程序的暂存器，用于评估梯形图或逻辑图或布尔表达式，BAM（40）中的源地址（“S”），其中初始 操作数被取消，存储操作结果的BAM（40）中的目的地地址（“D”）和存储目的地地址的目的地地址寄存器（“DAR”）（45）。 指令集包括输入指令的子集和结构指令的子集。 输入指令的操作数（I）是IOIM（25）中的地址。 结构指令的操作数（S，D）是BAM中的源和目的地址（40）。 每个输入指令从IOIM读取一个位的值，并具有将该位值逻辑组合到T寄存器中保留的值以及可能与BAM中的目标位的作用。 结构指令会对一对地址S和D进行操作，并且描述要编译的图的结构，或允许在图中的节点之间执行逻辑功能。

公开(公告)号：US08412566B2

公开(公告)日：2013-04-02

申请号：US10616486

申请日：2003-07-08

Applicant: Jesse T. Quatse ,  Anssi Karhinen ,  Eric G. Wasserman

Inventor： Jesse T. Quatse ,  Anssi Karhinen ,  Eric G. Wasserman

IPC: G06Q30/00

CPC classification number: G06Q30/0254 ,  G06Q30/02 ,  G06Q30/0211

Abstract: A system for distributing limited numbers of promotional offers to individual customers, the promotional offers being targeted to customers based on the customers' individual probabilities of accepting the offers in such a way that each customer can receive a limited number of offers that are estimated to be most likely to be acceptable by the customer. Customer-Based targeting analyzes each customer's past purchasing behavior relative to a master list of promotional offers made available to all customers. From that master list Customer-Based targeting selects a preset limit of promotional offers for each individual customer according to the likelihood that, given the opportunity to select any offers of the master list, each customer would prefer those few offers selected specifically for the customer. Various techniques are disclosed for providing an offer acceptance probability profile tailored for individual customers for use in the Customer-Based targeting technique. Product groupings and market segments are taken into account. Empirical Bayes techniques are applied to the estimation of the offer acceptance profile, and techniques suitable for handling sparse data are applied. Various marketing strategies are incorporated into the system. A graphical technique is provided for adjusting the offer acceptance profile that enables a user to override a system computation and manually set the relative offer acceptance probabilities for an individual user or class of users.

Abstract translation: 一种向个人客户分发有限数量的促销优惠的系统，根据客户的个人接受要约的方式，将促销优惠定位到客户，使得每个客户可以收到有限数量的优惠，估计是 最有可能被客户所接受。 基于客户的定位分析每个客户过去的采购行为相对于所有客户提供的促销优惠的主列表。 从该主列表中，基于客户的定位根据可能性，为每个客户选择预定的促销优惠限制，因为有机会选择主列表的任何优惠，每个客户都希望选择专门为客户选择的几个优惠。 公开了各种技术来提供为个人客户定制的报价接受概率概况，以用于基于客户的目标技术。 产品分组和市场细分被考虑在内。 经验贝叶斯技术被应用于报价接受概况的估计，并适用于处理稀疏数据的技术。 各种营销策略纳入系统。 提供了一种图形技术，用于调整报价接受简档，使得用户能够覆盖系统计算，并手动设置单个用户或一类用户的相对报价接受概率。

公开(公告)号：US4484307A

公开(公告)日：1984-11-20

申请号：US349285

申请日：1982-02-16

Applicant: Jesse T. Quatse ,  Donald E. Dodge, Jr. ,  Richard K. Dove

Inventor： Jesse T. Quatse ,  Donald E. Dodge, Jr. ,  Richard K. Dove

IPC: G06F11/14 ,  G06F11/20 ,  G07B17/00 ,  G06F15/20

CPC classification number: G07B17/00314 ,  G06F11/006 ,  G06F11/1441 ,  G07B2017/00338 ,  G07B2017/00346

Abstract: A microcomputerized postage meter that provides high degrees of security and fault tolerance. The meter maintains data security under low power conditions by the use of functionally nonvolatile memory units. Register and other data which must survive normal and abnormal losses of power to the meter electronics are stored in dual redundant battery augmented memories (hereinafter designated BAMs). Upon detecting an error condition, the microcomputer writes an appropriate fault code to the BAMs. A mechanism for disabling the meter includes dual redundant flip-flops which are set to a "faulted" state upon detection by the microcomputer of a failure condition. These flip-flops are powered by the BAM batteries. They cannot be reset except by physical access to the meter interior, which access is only available to authorized personnel at the factory. The fault flip-flops are also set when the microcomputer fails to properly execute its own operating program. Once the meter has been set to a "faulted" state, the fault flip-flops hold two signals, MPCLR ans SYSCLR, true. The BAM contents may still be read out independently of the microcomputer which is prevented from accessing the BAMs. This is accomplished by allowing power necessary to read the BAMs to be supplied to the BAMs without supplying power to the microcomputer. Moreover, even if the microcomputer is powered, MPCLR prevents it from executing instructions and SYSCLR isolates it.

Abstract translation: 一种提供高度安全性和容错能力的微电脑邮资计费器。 该仪表通过使用功能非易失性存储单元在低功耗条件下维护数据安全性。 寄存器和其他数据必须能够保持正常和异常的功率损失到仪表电子设备存储在双冗余电池增强存储器（以下称为BAM）中。 在检测到错误状况时，微机向BAM写入适当的故障代码。 用于禁用仪表的机构包括双重冗余触发器，其在由微型计算机检测到故障状态时被设置为“故障”状态。 这些触发器由BAM电池供电。 除了通过物理访问仪表内部之外，它们不能复位，只能在工厂授权的人员进行访问。 当微型计算机无法正确执行自己的操作程序时，也会设置故障触发器。 一旦仪表已经设置为“故障”状态，故障触发器将保持两个信号，MPCLR和SYSCLR为真。 仍然可以独立于无法访问BAM的微型计算机读出BAM内容。 这是通过允许在不向微型计算机供电的情况下读取提供给BAM的BAM所需的电力来实现的。 此外，即使微电脑供电，MPCLR阻止它执行指令，SYSCLR将其隔离。

公开(公告)号：US3555189A

公开(公告)日：1971-01-12

申请号：US3555189D

申请日：1967-11-20

Applicant: JESSE T QUATSE

Inventor： QUATSE JESSE T

IPC: G06F3/16 ,  H04M1/654 ,  H04M1/82 ,  H04M11/06 ,  H04M1/64

CPC classification number: H04M1/654 ,  G06F3/16 ,  H04M1/82 ,  H04M11/06

Abstract: An improved Automatic Telephone Answering Mechanism comprising a novel ring detector means which determines the proper time sequence of ringing detector means which determines the proper time sequence of ringing and silence by timing and logic circuit networks, thereby filtering out spurious telephone rings to automatically answer an associated telephone only when a true call is being made.

公开(公告)号：US4870614A

公开(公告)日：1989-09-26

申请号：US292623

申请日：1988-12-29

Applicant: Jesse T. Quatse

Inventor： Jesse T. Quatse

IPC: F02B75/02 ,  G05B19/05 ,  G06F9/305 ,  G06F9/38

CPC classification number: G06F9/30029 ,  G05B19/052 ,  G06F9/3879 ,  F02B2075/027

Abstract: A programmable controller architecture utilizes specialized processors in a co-processing system so that each function is optimized. The system comprises first and second processors having respective instruction sets and respective associated means for fetching instructions from a common memory. Each of the processors and its instruction set is tailored to a corresponding processor's specialized function. Each processor's instruction set includes a subset of special instructions, the occurrence of one of which signifies that control is to be passed from one processor to the other. Upon encountering a special instruction within its special instruction subset, a given processor invokes associated control passing circuitry for suspending its own operation and commencing the operation of the other processor. The passage of control occurs very quickly so that the speed benefits of switching control are not lost in the overhead of such switching. Since passage of control renders one of the processors inactive, there is no requirement that the actual instructions of one processor be objectively distinguishable from those of the other.

Abstract translation: 可编程控制器架构在协处理系统中使用专门的处理器，从而优化每个功能。 该系统包括具有相应指令集的第一和第二处理器以及用于从公共存储器读取指令的各自相关联的装置。 每个处理器及其指令集都是针对相应处理器的专门功能而定制的。 每个处理器的指令集包括一个特殊指令的子集，其中一个表示该控制将从一个处理器传递到另一个处理器。 在其特殊指令子集内遇到特殊指令时，给定的处理器调用相关联的控制传递电路来暂停其自己的操作并开始其他处理器的操作。 控制的过程非常快速地发生，从而在这种切换的开销中不会损失开关控制的速度优点。 由于控制通过使处理器中的一个不活动，所以不要求一个处理器的实际指令与另一个处理器的实际指令进行客观区分。

公开(公告)号：US4864531A

公开(公告)日：1989-09-05

申请号：US102255

申请日：1987-09-28

Applicant: Jesse T. Quatse ,  Lionel Heitz ,  Jacky Pergent ,  Olivier Penot

Inventor： Jesse T. Quatse ,  Lionel Heitz ,  Jacky Pergent ,  Olivier Penot

IPC: G05B19/02 ,  G05B9/02 ,  G05B19/04 ,  G05B19/048 ,  G05B19/05

CPC classification number: G05B19/054 ,  G05B2219/1159 ,  G05B2219/13188 ,  G05B2219/21149 ,  G05B2219/25152

Abstract: An input/output device monitors the transmission of information between a processor of a programmable controller and sensors and actuators of a process to be controlled. This device includes electronic circuits adapted for calculating the parities of the digital words which pass therethrough, these parities being compared with corresponding parities calculated by the processor which thereafter invalidates the words having two different parities.

Abstract translation: 输入/输出设备监视可编程控制器的处理器与要控制的过程的传感器和致动器之间的信息传输。 该装置包括适于计算通过其中的数字字的奇偶校验的电子电路，这些奇偶校验与由处理器计算的对应奇偶校验进行比较，其后使具有两个不同奇偶校验的单词无效。

公开(公告)号：US4683530A

公开(公告)日：1987-07-28

申请号：US598644

申请日：1984-04-10

Applicant: Jesse T. Quatse

Inventor： Jesse T. Quatse

IPC: G06F13/42

CPC classification number: G06F13/4291

Abstract: An interconnecting transparent serial bus for extending a parallel CPU domain to a parallel peripheral module domain includes a bidirectional serial protocol for transferring information between the CPU and one or more peripheral module controllers, referred to as rack masters. Each rack master provides a parallel path to any number of peripheral modules associated therewith. Serial bus protocol includes a frame line, defining a synchronous information exchange interval; a clock line, for propagating a synchronous information clock signal during the information exchange interval; a sync line, for propagating a sync signal to identify one or more discrete asynchronous information fields during the information exchange interval; and a signal line for propagating data, address, and control information between the CPU and its associated rack masters in serial fashion.

Abstract translation: 用于将并行CPU域扩展到并行外围模块域的互连透明串行总线包括用于在CPU和一个或多个外围模块控制器（称为机架主机）之间传送信息的双向串行协议。 每个机架主机提供到与其相关联的任何数量的外围模块的并行路径。 串行总线协议包括帧线，定义同步信息交换间隔; 时钟线，用于在信息交换间隔期间传播同步信息时钟信号; 同步线，用于在所述信息交换间隔期间传播同步信号以识别一个或多个离散异步信息字段; 以及用于以串行方式在CPU和其相关联的机架主机之间传播数据，地址和控制信息的信号线。