公开(公告)号：US6006348A

公开(公告)日：1999-12-21

申请号：US30917

申请日：1998-02-26

Applicant: Mikiko Sode ,  Yoichi Iizuka

Inventor： Mikiko Sode ,  Yoichi Iizuka

IPC: G01R31/28 ,  H03K3/037 ,  G06F11/06

CPC classification number: H03K3/0375

Abstract: A flip flop circuit for a scan test comprises a first latch circuit for latching and outputting data signal D in synchronization with control signal CLK when control signal SC1 is set at one level and latching and outputting scan in data signal SIN in synchronization with control signal SC1 when control signal CLK is set at the other level, and a second latch circuit for latching and outputting an output of the first latch circuit in synchronization with control signal CLK when control signal SC2 is set at one level and latching and outputting an output of the first latch circuit in synchronization with control signal SC2 when control signal CLK is set at the other level. In this way, the area of the circuit is decreased by commonly using one latch circuit for a data signal and a scan in data signal. Also, the skew adjustment is not required during a scan test by operating with two-phase clocks during both scan shift operation and scan normal operation.

Abstract translation: 用于扫描测试的触发器电路包括第一锁存电路，用于当控制信号SC1设置在一个电平时与控制信号CLK同步地锁存和输出数据信号D，并且与控制信号SC1同步地锁存和输出数据信号SIN中的扫描 当控制信号CLK被设置在另一个电平时，以及第二锁存电路，用于当控制信号SC2设置在一个电平时与控制信号CLK同步地锁存和输出第一锁存电路的输出，并锁存和输出第一锁存电路的输出 当控制信号CLK被设置在另一个电平时与控制信号SC2同步的第一锁存电路。 以这种方式，通过在数据信号中通常使用一个锁存电路和数据信号中的扫描来减小电路的面积。 此外，在扫描测试期间，通过在扫描移位操作和扫描正常操作期间通过使用两相时钟进行偏移调整。

公开(公告)号：US5392424A

公开(公告)日：1995-02-21

申请号：US897183

申请日：1992-06-11

Applicant: William B. Cook

Inventor： William B. Cook

IPC: G05B19/05 ,  G06F11/10 ,  G06F11/06 ,  H03M13/00

CPC classification number: G06F11/10 ,  G05B19/058 ,  G05B2219/13188 ,  G05B2219/14131 ,  G05B2219/15026

Abstract: A communication circuit sends asynchronous digital signals in parallel to an external device. A first parity circuit in the communication circuit computes a first bit which indicates the parity of the control signals. This first bit is sent to the external device. When the digital signals and the parity bit are received by the external device, a first control signal is produced when each of the received digital signals has the same logic level for a defined period of time. A second parity circuit produces a second control signal when a parity error is found in the received digital signals. An error signal is generated in response to the presence of both the first and second control signals.

Abstract translation: 通信电路将异步数字信号并行发送到外部设备。 通信电路中的第一奇偶校验电路计算指示控制信号奇偶校验的第一位。 该第一位被发送到外部设备。 当外部设备接收到数字信号和奇偶校验位时，当所接收的数字信号在规定的时间段内具有相同的逻辑电平时，产生第一控制信号。 当在所接收的数字信号中发现奇偶校验错误时，第二奇偶校验电路产生第二控制信号。 响应于第一和第二控制信号的存在而产生误差信号。

公开(公告)号：US4204114A

公开(公告)日：1980-05-20

申请号：US880876

申请日：1978-02-24

Applicant: William E. Shoemaker ,  David W. Wilson

Inventor： William E. Shoemaker ,  David W. Wilson

IPC: G01R31/3177 ,  G06F11/25 ,  G06F11/277 ,  G06F11/06 ,  G01R15/12

CPC classification number: G01R31/3177 ,  G06F11/25 ,  G06F11/277

Abstract: Techniques for displaying on a cathode ray tube a plurality of logic signals either from a single electronic circuit under test wherein the signals are acquired by a single probe, or in comparison to signals from a known good electronic circuit of the same type wherein compensation is provided to eliminate differences in the logic signals that are due to differences in the timing signal frequencies of the two circuits.

Abstract translation: 用于在阴极射线管上显示来自被测单个电子电路的多个逻辑信号的技术，其中信号由单个探针获取，或者与来自已提供补偿的已知良好电子电路的信号相比较 以消除由于两个电路的定时信号频率的差异导致的逻辑信号的差异。

公开(公告)号：US4187540A

公开(公告)日：1980-02-05

申请号：US870546

申请日：1978-01-18

Applicant: Thomas T. Davis ,  Marvin C. Burk

Inventor： Thomas T. Davis ,  Marvin C. Burk

IPC: G06F11/267 ,  G06F11/06 ,  G06F3/02 ,  G06F3/14

CPC classification number: G06F11/2221

Abstract: A control panel which provides an interface to a digital computer, and which comprises at least a data input device such as a keyboard and a data output device such as an alphanumeric display or a light emitting diode display, is tested without the use of the digital computer. The digital computer is disconnected or bypassed and the timing and other functions of the computer are simulated to enable an independent test of the data input device and the data output device which make up at least a part of the control panel.

Abstract translation: 提供与数字计算机的接口并且至少包括诸如键盘的数据输入设备和诸如字母数字显示器或发光二极管显示器的数据输出设备的控制面板被测试，而不使用数字 电脑。 数字计算机断开或旁路，并且模拟计算机的定时和其他功能，以便对构成控制面板的至少一部分的数据输入设备和数据输出设备进行独立测试。

公开(公告)号：US3810120A

公开(公告)日：1974-05-07

申请号：US11487671

申请日：1971-02-12

Applicant: HONEYWELL INF SYSTEMS

Inventor： HUETTNER R ,  TYMANN E

IPC: G06F11/00 ,  G06F11/07 ,  G06F13/42 ,  G06F11/06 ,  G05B13/02 ,  G06K17/00

CPC classification number: G06F11/0757 ,  G06F11/0745 ,  G06F11/0793 ,  G06F13/4217

Abstract: An apparatus is associated with scanning apparatus for a number of peripheral input and output devices connected to a common input/output bus of a terminal system. The apparatus includes means for detecting a failure in any one of the peripheral devices by monitoring the condition of the terminal bus. Upon detecting the presence of a failed device on the bus, the apparatus then determines automatically whether the device is operating as an input or output device and thereafter selectively disables the failed device whereby the terminal system is placed in a state in which it can still continue system data transfer operations.

Abstract translation: 一种装置与连接到终端系统的公共输入/输出总线的多个外围输入和输出装置的扫描装置相关联。 该装置包括通过监视终端总线的状况来检测任何一个外围设备中的故障的装置。 当检测到总线上出现故障的设备时，设备然后自动地确定设备是否正在作为输入或输出设备操作，并且此后选择性地禁用故障设备，由此终端系统处于仍然可以继续的状态 系统数据传输操作。

公开(公告)号：US3673577A

公开(公告)日：1972-06-27

申请号：US3673577D

申请日：1971-01-25

Applicant: ERICSSON TELEFON AB L M

Inventor： EDSTROM NILS HERBERT ,  HEMDAL GORAN ANDERS HENRIK

IPC: G06F17/00 ,  H04Q3/545 ,  G05B23/02 ,  G06F11/06

CPC classification number: H04Q3/54591

Abstract: A process control computer scans test points arranged in groups to perform operations in accordance with changes in the states of the test points. The data store of the computer stores the states of the test points as words wherein each work represents a group of test points and the bits of the words represent the test points of the group. A flag resister of the data store comprises a group of bit cells with each bit cell being associated with one of the words. During the scan if the change of state of a test point changes, the associated bit in the data store is changed and the flange bit of the associated word is marked. Thereafter, the computer need only scan those words whose flag bits have been marked.

Abstract translation: 过程控制计算机扫描分组排列的测试点，以根据测试点状态的变化进行操作。 计算机的数据存储器将测试点的状态存储为单词，其中每个工作表示一组测试点，并且单词的位表示组的测试点。 数据存储器的标志寄存器包括一组位单元，其中每个位单元与一个单词相关联。 在扫描期间如果测试点的状态改变，数据存储器中的关联位被改变，并且相关联的字的法兰位被标记。 此后，计算机只需扫描标记位被标记的那些字。

公开(公告)号：US3644936A

公开(公告)日：1972-02-22

申请号：US3644936D

申请日：1970-01-23

Applicant: BOOLE & BABBAGE INC

Inventor： HOLTWICK GARY M ,  KOLENCE KENNETH W

IPC: G06F11/34 ,  G06F9/19 ,  G05B23/02 ,  G06F7/02 ,  G06F11/06

CPC classification number: G06F11/3423

Abstract: Apparatus and method for determining how a computer program is performing by sampling the operative conditions of a number of operating elements of a computer, such as the elements of the processing unit and the memory thereof. The information obtained from such sampling can be used to establish whether the program is ''''waiting,'''' ''''executing'''' or ''''actively computing.'''' Thus, a review of this information can be used to determine if the computer is being adequately utilized by the program and, if not, how it can be more efficiently utilized. The information is extracted randomly during the execution of the program following which the information is categorized and read out so as to be in an observable form.

公开(公告)号：US4799220A

公开(公告)日：1989-01-17

申请号：US16685

申请日：1987-02-19

Applicant: Robert E. Nielsen

Inventor： Robert E. Nielsen

IPC: G06F11/22 ,  G01R31/319 ,  G01R31/3193 ,  G06F11/06

CPC classification number: G01R31/31919 ,  G01R31/31935

Abstract: An automatic testing instrument determines the operational status of an equipment under test on a real time basis by first generating from a stimulus memory a pattern for stimulating the equipment which, when stimulated by the pattern, sends out a response pattern, which is transmitted back to the automatic testing instrument. The testing instrument then takes the received response pattern and compares it with a pre-determined pattern stored in a comparator. If the response pattern differs from the expected pattern, an error signal is sent to indicate to the user of the testing instrument that the equipment under test is operating erroneously, for that particular pattern.

Abstract translation: 自动测试仪器通过首先从刺激存储器产生用于刺激设备的模式来确定被测设备的操作状态，该模式在被模式刺激时发出响应模式，该响应模式被传送回 自动检测仪器。 然后，测试仪器接收接收到的响应模式并将其与存储在比较器中的预定模式进行比较。 如果响应模式与预期模式不同，则发送错误信号以向测试仪器的用户指示被测设备错误地操作该特定模式。

公开(公告)号：US4219875A

公开(公告)日：1980-08-26

申请号：US903103

申请日：1978-05-05

Applicant: Steven R. Templeton

Inventor： Steven R. Templeton

IPC: G06F13/22 ,  G06F17/40 ,  G06F11/06 ,  G06F15/46

CPC classification number: G06F13/22

Abstract: A computer based process control system includes a digital event counter input circuit wherein a number of data sources are scanned. A sensed status of the individual input point is compared with the previous status of that point to determine if a change of status has occurred, indicative of an event to be counted. The previous status is stored in a dedicated register. If the comparison indicates that a countable event has occurred, a counter is incremented; also the dedicated register is updated to indicate the present status of the scanned point. The counter status is stored in an accompanying memory which may then be read out by an external device such as a processor.

Abstract translation: 基于计算机的过程控制系统包括数字事件计数器输入电路，其中扫描多个数据源。 将感测到的个体输入点的状态与该点的先前状态进行比较，以确定是否已经发生状态改变，表示要计数的事件。 先前的状态存储在专用寄存器中。 如果比较表明可数事件发生，计数器会增加; 还会更新专用寄存器以指示扫描点的当前状态。 计数器状态存储在伴随的存储器中，然后可以由诸如处理器的外部设备读出。

公开(公告)号：US4208715A

公开(公告)日：1980-06-17

申请号：US892127

申请日：1978-03-31

Applicant: Mitsuo Kumahara ,  Takatoshi Ishii

Inventor： Mitsuo Kumahara ,  Takatoshi Ishii

IPC: G06F1/26 ,  G06F11/20 ,  G06F15/16 ,  H02J9/06 ,  G06F11/06 ,  G06F3/02

CPC classification number: G06F11/20

Abstract: A dual data processing system comprising a first data processing unit having a first control unit and a first logic switching circuit; a second control unit having a second logic switching circuit; a pair of switch circuits coupled to the first and second logic switching circuits, respectively; adapter buffers to be coupled selectively to the first and second control units according to the operation of the switch circuits; a first power source for supplying electric power to the first control unit and the adapter buffers coupled thereto; and a second power source for supplying electric power to the second control unit and the adapter buffers coupled thereto. The switch circuits are operated to connect the adapter buffers selectively to the first and second control units so that load balance is kept between the first and second control units.

Abstract translation: 一种双数据处理系统，包括具有第一控制单元和第一逻辑切换电路的第一数据处理单元; 第二控制单元，具有第二逻辑切换电路; 一对开关电路，分别耦合到第一和第二逻辑开关电路; 适配器缓冲器根据开关电路的操作选择性地耦合到第一和第二控制单元; 用于向第一控制单元提供电力的第一电源和与其耦合的适配器缓冲器; 以及用于向第二控制单元和耦合到其的适配器缓冲器提供电力的第二电源。 开关电路被操作以将适配器缓冲器选择性地连接到第一和第二控制单元，从而在第一和第二控制单元之间保持负载平衡。