公开(公告)号：US20110239174A1

公开(公告)日：2011-09-29

申请号：US13071076

申请日：2011-03-24

Applicant: Mikiko SODE

Inventor： Mikiko SODE

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F2217/78

Abstract: A method for laying out a power wiring of a semiconductor device including an analog circuit and a digital circuit includes: modeling the power wiring as an analysis model including a plurality of nodes and a plurality of element resistors provided between the plurality of nodes neighboring each other; obtaining voltage values of the plurality of nodes by a circuit simulation; searching a maximum current node from nodes of the digital circuit when a substrate noise violation exists in a voltage value of a node of the analog circuit, the maximum current node having a maximum amount of current flowing into the node of the analog circuit; searching a path of a current flowing into the maximum current node in the digital circuit; selecting a bottleneck element resistor from among the plurality of element resistors included in the path; and changing a resistance value of the bottleneck element resistor.

Abstract translation: 一种用于布置包括模拟电路和数字电路的半导体器件的电源布线的方法，包括：将功率布线建模为包括多个节点的分析模型和设置在彼此相邻的多个节点之间的多个元件电阻 ; 通过电路仿真获得多个节点的电压值; 当在所述模拟电路的节点的电压值中存在衬底噪声冲突时，从所述数字电路的节点搜索最大电流节点，所述最大电流节点具有流入所述模拟电路的节点的最大电流量; 搜索流入数字电路中的最大电流节点的电流的路径; 从包括在所述路径中的所述多个元件电阻器中选择瓶颈元件电阻器; 并改变瓶颈元件电阻的电阻值。

公开(公告)号：US6006348A

公开(公告)日：1999-12-21

申请号：US30917

申请日：1998-02-26

Applicant: Mikiko Sode ,  Yoichi Iizuka

Inventor： Mikiko Sode ,  Yoichi Iizuka

IPC: G01R31/28 ,  H03K3/037 ,  G06F11/06

CPC classification number: H03K3/0375

Abstract: A flip flop circuit for a scan test comprises a first latch circuit for latching and outputting data signal D in synchronization with control signal CLK when control signal SC1 is set at one level and latching and outputting scan in data signal SIN in synchronization with control signal SC1 when control signal CLK is set at the other level, and a second latch circuit for latching and outputting an output of the first latch circuit in synchronization with control signal CLK when control signal SC2 is set at one level and latching and outputting an output of the first latch circuit in synchronization with control signal SC2 when control signal CLK is set at the other level. In this way, the area of the circuit is decreased by commonly using one latch circuit for a data signal and a scan in data signal. Also, the skew adjustment is not required during a scan test by operating with two-phase clocks during both scan shift operation and scan normal operation.

Abstract translation: 用于扫描测试的触发器电路包括第一锁存电路，用于当控制信号SC1设置在一个电平时与控制信号CLK同步地锁存和输出数据信号D，并且与控制信号SC1同步地锁存和输出数据信号SIN中的扫描 当控制信号CLK被设置在另一个电平时，以及第二锁存电路，用于当控制信号SC2设置在一个电平时与控制信号CLK同步地锁存和输出第一锁存电路的输出，并锁存和输出第一锁存电路的输出 当控制信号CLK被设置在另一个电平时与控制信号SC2同步的第一锁存电路。 以这种方式，通过在数据信号中通常使用一个锁存电路和数据信号中的扫描来减小电路的面积。 此外，在扫描测试期间，通过在扫描移位操作和扫描正常操作期间通过使用两相时钟进行偏移调整。

公开(公告)号：US08205184B2

公开(公告)日：2012-06-19

申请号：US13071076

申请日：2011-03-24

Applicant: Mikiko Sode

Inventor： Mikiko Sode

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5077 ,  G06F2217/78

Abstract: A method for laying out a power wiring of a semiconductor device including an analog circuit and a digital circuit includes: modeling the power wiring as an analysis model including a plurality of nodes and a plurality of element resistors provided between the plurality of nodes neighboring each other; obtaining voltage values of the plurality of nodes by a circuit simulation; searching a maximum current node from nodes of the digital circuit when a substrate noise violation exists in a voltage value of a node of the analog circuit, the maximum current node having a maximum amount of current flowing into the node of the analog circuit; searching a path of a current flowing into the maximum current node in the digital circuit; selecting a bottleneck element resistor from among the plurality of element resistors included in the path; and changing a resistance value of the bottleneck element resistor.

Abstract translation: 一种用于布置包括模拟电路和数字电路的半导体器件的电源布线的方法，包括：将功率布线建模为包括多个节点的分析模型和设置在彼此相邻的多个节点之间的多个元件电阻 ; 通过电路仿真获得多个节点的电压值; 当在所述模拟电路的节点的电压值中存在衬底噪声冲突时，从所述数字电路的节点搜索最大电流节点，所述最大电流节点具有流入所述模拟电路的节点的最大电流量; 搜索流入数字电路中的最大电流节点的电流的路径; 从包括在所述路径中的所述多个元件电阻器中选择瓶颈元件电阻器; 并改变瓶颈元件电阻的电阻值。

公开(公告)号：US08375346B2

公开(公告)日：2013-02-12

申请号：US13070500

申请日：2011-03-24

Applicant: Mikiko Sode

Inventor： Mikiko Sode

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5077

Abstract: An aspect of the present invention is a method for laying out a power wiring of a semiconductor device. The method includes: modeling the power wiring as an analysis model including a plurality of nodes and a plurality of element resistors provided between the plurality of nodes neighboring each other; obtaining voltage values of the plurality of nodes by a circuit simulation; searching a path of a current flowing into a node of the plurality of nodes when an IR drop violation exists in the voltage values, the node having a maximum value of the IR drop violation; selecting a bottleneck element resistor from among the plurality of element resistors included in the path; and changing a resistance value of the bottleneck element resistor.

Abstract translation: 本发明的一个方面是一种布置半导体器件的电源布线的方法。 该方法包括：将电力线路建模为包括多个节点之间的分析模型和设置在彼此相邻的多个节点之间的多个元件电阻器; 通过电路仿真获得多个节点的电压值; 当所述电压值中存在IR丢弃冲突时，搜索流入所述多个节点的节点的电流的路径，所述节点具有所述IR丢弃违例的最大值; 从包括在所述路径中的所述多个元件电阻器中选择瓶颈元件电阻器; 并改变瓶颈元件电阻的电阻值。

公开(公告)号：US20110239180A1

公开(公告)日：2011-09-29

申请号：US13070500

申请日：2011-03-24

Applicant: MIKIKO SODE

Inventor： MIKIKO SODE

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5077

Abstract: An aspect of the present invention is a method for laying out a power wiring of a semiconductor device. The method includes: modeling the power wiring as an analysis model including a plurality of nodes and a plurality of element resistors provided between the plurality of nodes neighboring each other; obtaining voltage values of the plurality of nodes by a circuit simulation; searching a path of a current flowing into a node of the plurality of nodes when an IR drop violation exists in the voltage values, the node having a maximum value of the IR drop violation; selecting a bottleneck element resistor from among the plurality of element resistors included in the path; and changing a resistance value of the bottleneck element resistor

Abstract translation: 本发明的一个方面是一种布置半导体器件的电源布线的方法。 该方法包括：将电力线路建模为包括多个节点之间的分析模型和设置在彼此相邻的多个节点之间的多个元件电阻器; 通过电路仿真获得多个节点的电压值; 当所述电压值中存在IR丢弃冲突时，搜索流入所述多个节点的节点的电流的路径，所述节点具有所述IR丢弃违例的最大值; 从包括在所述路径中的所述多个元件电阻器中选择瓶颈元件电阻器; 并改变瓶颈元件电阻的电阻值