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公开(公告)号：US12027380B2
公开(公告)日：2024-07-02
申请号：US17464007
申请日：2021-09-01
IPC分类号： H01L21/67 , H01L21/02 , H01L21/306 , H01L21/687
CPC分类号： H01L21/67017 , H01L21/02041 , H01L21/306 , H01L21/67057 , H01L21/67086 , H01L21/68771 , H01L21/6708
摘要： In one embodiment, a semiconductor manufacturing apparatus includes a substrate holder configured to hold a plurality of substrates such that the substrates are arranged in parallel to each other. The apparatus further includes a fluid injector including a plurality of openings that inject fluid to areas in which distances from surfaces of the substrates are within distances between centers of the substrates adjacent to each other, the fluid injector being configured to change injection directions of the fluid injected from the openings in planes that are parallel to the surfaces of the substrates by self-oscillation.
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公开(公告)号：US11348934B2
公开(公告)日：2022-05-31
申请号：US17182879
申请日：2021-02-23
发明人： Takehiko Amaki , Yoshihisa Kojima , Toshikatsu Hida , Marie Grace Izabelle Angeles Sia , Riki Suzuki , Shohei Asami
IPC分类号： H01L27/11556 , G11C16/08 , G11C16/10 , G11C16/04 , G11C16/16 , G11C7/04 , G11C16/26 , H01L27/1157 , H01L27/11582
摘要： According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.
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公开(公告)号：US20220108754A1
公开(公告)日：2022-04-07
申请号：US17554710
申请日：2021-12-17
发明人： Masanobu SHIRAKAWA
IPC分类号： G11C16/26 , G11C11/56 , H01L27/1157 , G11C7/06 , G11C16/34 , H01L27/11582 , G11C16/10
摘要： According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first blocks including a memory cell capable of storing data of one bit, a second block including a memory cell capable of storing data of two or more bits. The semiconductor memory stores first data in a first latch circuit, and second data in a second latch circuit, and writes the first data into one of the first blocks in page units, and the second data into one of the first blocks in page units. The semiconductor memory writes data of at least two pages into the second block, using the first data stored in the first latch circuit and the second data stored in the second latch circuit.
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公开(公告)号：US20220107761A1
公开(公告)日：2022-04-07
申请号：US17554092
申请日：2021-12-17
发明人： Shinichi KANNO
摘要： According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of blocks. The controller is electrically coupled to the nonvolatile memory. The controller controls the nonvolatile memory. When receiving, from the host, a first command for changing a state of an allocated block to a reallocatable state in a case where a second command that is yet to be executed or being executed involving read of data from the allocated block has been received from the host, the controller changes the state of the allocated block to the reallocatable state after the second command is finished.
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公开(公告)号：US20220102262A1
公开(公告)日：2022-03-31
申请号：US17545709
申请日：2021-12-08
发明人： Takayuki TAJIMA , Kazuo SHIMOKAWA
IPC分类号： H01L23/498 , H01L23/00 , H01L21/683 , H01L21/48 , H01L25/065
摘要： A semiconductor device includes an insulating layer, a conductive member provided inside the insulating layer, a chip disposed on a first surface of the insulating layer and connected to the conductive member, and an electrode connected to the conductive member via a barrier layer. A resistivity of the barrier layer is higher than a resistivity of the conductive member. At least a portion of the electrode protrudes from a second surface of the insulating layer.
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公开(公告)号：US20220084846A1
公开(公告)日：2022-03-17
申请号：US17532074
申请日：2021-11-22
发明人： Hidekazu HAYASHI
IPC分类号： H01L21/67 , H01L21/306
摘要： A semiconductor manufacturing apparatus includes a mounting unit arranged to mount an annular member, having an annular shape, to a work substrate including a first substrate and a second substrate bonded to each other so that the annular member surrounds the first substrate. The apparatus further includes a holding unit arranged to hold the work substrate having the annular member mounted thereto. The apparatus further includes a first fluid supply unit arranged to supply a first fluid to the second substrate of the work substrate held by the holding unit.
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公开(公告)号：US20220066676A1
公开(公告)日：2022-03-03
申请号：US17521552
申请日：2021-11-08
发明人： Yaron KLEIN
摘要： A method of managing data storage using a management device that includes determining respective status information for a plurality of storage devices, and calculating, based on the status information, a respective cost for each of the plurality of storage devices using a cost function that includes one or more parameters including at least one of: a program/erase (P/E) parameter, a block error state parameter, a block error level parameter, and a workload parameter. The method further includes selecting a destination storage device of the plurality of storage devices based on at least some of the calculated costs, and writing data to the destination storage device.
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公开(公告)号：US20220055254A1
公开(公告)日：2022-02-24
申请号：US17518929
申请日：2021-11-04
发明人： Kei KOBAYASHI , Anupam MITRA , Seiji MORITA , Hirokazu KATO
摘要： According to one embodiment, a template for imprint patterning processes comprises a template substrate having a first surface and a pedestal on the first surface of the template substrate, the pedestal having a second surface spaced from the first surface in a first direction perpendicular to the first surface. A pattern is disposed on the second surface. The pedestal has a sidewall between the first surface and the second surface that is at an angle of less than 90° to the second surface.
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公开(公告)号：US11256947B2
公开(公告)日：2022-02-22
申请号：US16565774
申请日：2019-09-10
发明人： Mitsuyo Asano
IPC分类号： G06K9/46 , H01J37/244 , G03F1/38
摘要： According to one embodiment, an image data of a measurement object including a pattern is acquired. First data is acquired by extracting a contour of an element in composition of the pattern from the image data. Second data that specifies a design data of the measurement object and the pattern of the measurement object is acquired. The design data includes a pattern data. A measurement pattern is extracted by using the first data and the second data. An evaluation value for the measurement pattern with respect to the design data is calculated based on the difference between the measurement pattern and the design data.
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公开(公告)号：US20220037217A1
公开(公告)日：2022-02-03
申请号：US17503947
申请日：2021-10-18
发明人： Naoki YAMAMOTO , Yu HIROTSU
IPC分类号： H01L21/66 , H01L21/768 , H01L27/11565 , H01L27/11575 , H01L27/11582
摘要： A semiconductor memory according to an embodiment includes first and second areas, an active region, a non-active region, a first stacked body, a plurality of first pillars, a first contact, a second stacked body, and a second contact. The active region includes part of each of the first and second areas. The non-active region includes part of each of the first and second areas. The second stacked body is in the non-active region. The second stacked body includes second insulators and second conductors which are alternately stacked. A second contact is in contact with a second conductor in a first interconnect layer and a second conductor in a second interconnect layer.
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