知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

1512 条记录 (耗时 0.02 秒)

    LATERAL BIPOLAR TRANSISTORS
    1.
    发明公开
    LATERAL BIPOLAR TRANSISTORS 审中-公开

    公开(公告)号：US20240363741A1

    公开(公告)日：2024-10-31

    申请号：US18767418

    申请日：2024-07-09

    申请人： GLOBALFOUNDRIES U.S. Inc.

    发明人： Jagar SINGH

    IPC分类号： H01L29/735 ,  H01L29/08 ,  H01L29/10

    CPC分类号： H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008

    摘要： The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an emitter in a semiconductor substrate; a collector in the semiconductor substrate; a base contact region in the semiconductor substrate and adjacent to the collector and the emitter; and a shallow trench isolation structure overlapping the base contact region and separating the base contact region from the emitter and the collector.

    Semiconductor structure with semiconductor-on-insulator region and method
    3.
    发明授权
    Semiconductor structure with semiconductor-on-insulator region and method 有权

    公开(公告)号：US12131904B2

    公开(公告)日：2024-10-29

    申请号：US17934220

    申请日：2022-09-22

    申请人： GlobalFoundries U.S. Inc.

    发明人： Ramsey Hazbun ,  Alvin J. Joseph ,  Siva P. Adusumilli ,  Cameron Luce

    IPC分类号： H01L21/02

    CPC分类号： H01L21/02433 ,  H01L21/02381 ,  H01L21/02639 ,  H01L21/02647

    摘要： Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.

    Bias voltage generation circuit for memory devices
    9.
    发明授权
    Bias voltage generation circuit for memory devices 有权

    公开(公告)号：US12087384B2

    公开(公告)日：2024-09-10

    申请号：US17668962

    申请日：2022-02-10

    申请人： GLOBALFOUNDRIES U.S. Inc.

    发明人： Ming Yin ,  Bipul C. Paul ,  Nishtha Gaul ,  Shashank Nemawarkar

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147 ,  G11C5/148

    摘要： The present disclosure relates to memory devices and, more particularly, to bias voltage generation circuit for memory devices and methods of operation. The voltage generation circuit includes: an internal voltage generator which providing a bias voltage to at least one internal node of a bias voltage generation circuitry; and at least one pre-charging circuitry providing a predefined bias voltage to at least one internal node including a distributed network of local drivers.