Device and method for reducing impedance
    1.
    发明授权
    Device and method for reducing impedance 有权
    降低阻抗的装置和方法

    公开(公告)号:US08564967B2

    公开(公告)日:2013-10-22

    申请号:US11949329

    申请日:2007-12-03

    IPC分类号: H05K1/16

    摘要: A printed wiring board semiconductor package or PWB power core comprising singulated capacitors embedded on multiple layers of the printed wiring board semiconductor package wherein at least a part of each embedded capacitor lies within the die shadow and wherein the embedded, singulated capacitors comprise at least a first electrode and a second electrode. The first electrodes and second electrodes of the embedded singulated capacitors are interconnected to the Vcc (power) terminals and the Vss (ground) terminals respectively of a semiconductor device. The size of the embedded capacitors are varied to produce different self-resonant frequencies and their vertical placements within the PWB semiconductor package are used to control the inherent inductance of the capacitor-semiconductor electrical interconnections so that customized resonant frequencies of the embedded capacitors can be achieved with low impedance.

    摘要翻译: 一种印刷线路板半导体封装或PWB功率核,其包括嵌入在所述印刷线路板半导体封装的多层上的单片电容器,其中每个嵌入式电容器的至少一部分位于所述管芯阴影内,并且其中所述嵌入式单片电容器包括至少第一 电极和第二电极。 嵌入式单片电容器的第一电极和第二电极分别与半导体器件的Vcc(功率)端子和Vss(接地)端子互连。 嵌入式电容器的尺寸变化以产生不同的自谐振频率,并且它们在PWB半导体封装内的垂直布置用于控制电容器 - 半导体电互连的固有电感,从而可以实现嵌入式电容器的定制谐振频率 具有低阻抗。