公开(公告)号：US07613007B2

公开(公告)日：2009-11-03

申请号：US11289994

申请日：2005-11-30

Applicant: Daniel Irwin Amey, Jr. ,  Sounak Banerji ,  William J. Borland ,  Karl Hartmann Dietz ,  David Ross McGregor ,  Attiganal N. Sreeram

Inventor： Daniel Irwin Amey, Jr. ,  Sounak Banerji ,  William J. Borland ,  Karl Hartmann Dietz ,  David Ross McGregor ,  Attiganal N. Sreeram

IPC: H05K1/18

CPC classification number: H01L23/66 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09763 ,  H01L2224/0401

Abstract: The present invention relates to a device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor; and at least one planar capacitor laminate; wherein said planar capacitor laminate serves as a low inductance path to supply a charge to said at least one embedded singulated capacitor; and wherein said at least one embedded singulated capacitor is connected in parallel to at least one of the said planar capacitor laminates; and wherein said power core is interconnected to at least one signal layer.

Abstract translation: 本发明涉及一种包括功率核心的器件，其中所述功率核心包括：至少一个嵌入的单个电容器层，其包含至少一个嵌入式单电容器; 和至少一个平面电容器层压体; 其中所述平面电容器层叠体用作低电感路径以向所述至少一个嵌入式分离电容器提供电荷; 并且其中所述至少一个嵌入式单电容器与所述平面电容器层压体中的至少一个并联连接; 并且其中所述功率核心与至少一个信号层相互连接。

公开(公告)号：US08564967B2

公开(公告)日：2013-10-22

申请号：US11949329

申请日：2007-12-03

Applicant: Daniel Irwin Amey, Jr. ,  William J. Borland

Inventor： Daniel Irwin Amey, Jr. ,  William J. Borland

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H01L2224/16225 ,  H05K1/112 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09763 ,  H05K2201/10674

Abstract: A printed wiring board semiconductor package or PWB power core comprising singulated capacitors embedded on multiple layers of the printed wiring board semiconductor package wherein at least a part of each embedded capacitor lies within the die shadow and wherein the embedded, singulated capacitors comprise at least a first electrode and a second electrode. The first electrodes and second electrodes of the embedded singulated capacitors are interconnected to the Vcc (power) terminals and the Vss (ground) terminals respectively of a semiconductor device. The size of the embedded capacitors are varied to produce different self-resonant frequencies and their vertical placements within the PWB semiconductor package are used to control the inherent inductance of the capacitor-semiconductor electrical interconnections so that customized resonant frequencies of the embedded capacitors can be achieved with low impedance.

Abstract translation: 一种印刷线路板半导体封装或PWB功率核，其包括嵌入在所述印刷线路板半导体封装的多层上的单片电容器，其中每个嵌入式电容器的至少一部分位于所述管芯阴影内，并且其中所述嵌入式单片电容器包括至少第一 电极和第二电极。 嵌入式单片电容器的第一电极和第二电极分别与半导体器件的Vcc（功率）端子和Vss（接地）端子互连。 嵌入式电容器的尺寸变化以产生不同的自谐振频率，并且它们在PWB半导体封装内的垂直布置用于控制电容器 - 半导体电互连的固有电感，从而可以实现嵌入式电容器的定制谐振频率 具有低阻抗。

公开(公告)号：US07778038B2

公开(公告)日：2010-08-17

申请号：US11289961

申请日：2005-11-30

Applicant: David Ross McGregor ,  Daniel Irwin Amey, Jr. ,  Sounak Banerji ,  William J. Borland ,  Karl Hartmann Dietz ,  Attiganal N. Sreeram

Inventor： David Ross McGregor ,  Daniel Irwin Amey, Jr. ,  Sounak Banerji ,  William J. Borland ,  Karl Hartmann Dietz ,  Attiganal N. Sreeram

IPC: H05K1/18

CPC classification number: H05K1/186 ,  H05K1/0231 ,  H05K1/162 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/10636 ,  Y02P70/611

Abstract: The present invention relates to a power core comprising: at least one embedded surface mount technology (SMT) discrete chip capacitor layer comprising at least one embedded SMT discrete chip capacitor; and at least one planar capacitor laminate; wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded SMT discrete chip capacitor; and wherein said embedded SMT discrete chip capacitor is connected in parallel to said planar capacitor laminate.

Abstract translation: 电源核心技术领域本发明涉及一种功率核心，包括：至少一个嵌入式表面贴装技术（SMT）离散芯片电容器层，包括至少一个嵌入式SMT分立片式电容器; 和至少一个平面电容器层压板; 其中至少一个平面电容器层叠体用作低电感路径以向至少一个嵌入式SMT分立片式电容器提供电荷; 并且其中所述嵌入式SMT分立片式电容器与所述平面电容层叠体并联连接。

公开(公告)号：US07531416B2

公开(公告)日：2009-05-12

申请号：US11313562

申请日：2005-12-21

Applicant: Daniel Irwin Amey, Jr. ,  William J. Borland

Inventor： Daniel Irwin Amey, Jr. ,  William J. Borland

IPC: H01L21/8222

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01G4/33 ,  H01L23/50 ,  H01L23/66 ,  H01L27/013 ,  H01L2924/0002 ,  H01L2924/19103 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/162 ,  H05K2201/09763 ,  H05K2201/10515 ,  H05K2201/10689 ,  H01L2924/00

Abstract: Thick-film capacitors are formed on ceramic interconnect substrates having high capacitance densities and other desirable electrical and physical properties. The capacitor dielectrics are fired at high temperatures.

Abstract translation: 在具有高电容密度和其它所需电气和物理特性的陶瓷互连基板上形成厚膜电容器。 电容器电介质在高温下烧制。

公开(公告)号：US20100037951A1

公开(公告)日：2010-02-18

申请号：US12539677

申请日：2009-08-12

Applicant: William J. Borland ,  Howard David Glicksman

Inventor： William J. Borland ,  Howard David Glicksman

IPC: H01L31/042 ,  B22F9/08 ,  B22F1/02

CPC classification number: B22F9/24 ,  B22F1/0048 ,  B22F9/28 ,  B22F2998/10 ,  B22F2999/00 ,  H01B1/22 ,  H01L31/022425 ,  H01L31/18 ,  Y02E10/50 ,  Y02E10/52 ,  B22F9/026 ,  B22F9/30 ,  B22F2201/02 ,  B22F2201/10 ,  B22F2201/01 ,  B22F2201/013

Abstract: Disclosed are methods of making multi-element, finely divided, metal powders containing one or more reactive metals and one or more non-reactive metals. Reactive metals include metals or mixtures thereof from titanium (Ti), zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb), vanadium (V), nickel (Ni), cobalt (Co), molybdenum (Mo), manganese (Mn), and iron (Fe). Non-reactive metals include metals or mixtures such as silver (Ag), tin (Sn), bismuth (Bi), lead (Pb), antimony (Sb), zinc (Zn), germanium (Ge), phosphorus (P), gold (Au), cadmium (Cd), berrylium (Be), tellurium (Te).

Abstract translation: 公开了制备含有一种或多种反应性金属和一种或多种非反应性金属的多元素细碎金属粉末的方法。 反应性金属包括钛（Ti），锆（Zr），铪（Hf），钽（Ta），铌（Nb），钒（V），镍（Ni），钴（Co） Mo），锰（Mn）和铁（Fe）。 非反应性金属包括银（Ag），锡（Sn），铋（Bi），铅（Pb），锑（Sb），锌（Zn），锗（Ge），磷（P） 金（Au），镉（Cd），铍（Be），碲（Te）。

公开(公告)号：US07586198B2

公开(公告)日：2009-09-08

申请号：US11321934

申请日：2005-12-29

Applicant: William J. Borland ,  Saul Ferguson ,  Diptarka Majumdar ,  Matthew C. Snogren ,  Richard H. Snogren

Inventor： William J. Borland ,  Saul Ferguson ,  Diptarka Majumdar ,  Matthew C. Snogren ,  Richard H. Snogren

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K3/4679 ,  H01L2224/16225 ,  H05K1/0269 ,  H05K1/092 ,  H05K1/162 ,  H05K1/167 ,  H05K3/0082 ,  H05K3/064 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09063 ,  H05K2201/09763 ,  H05K2201/09918 ,  H05K2203/0338 ,  H05K2203/167 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49146 ,  Y10T29/49156

Abstract: Innerlayer panels are provided with high density fiducials during manufacture. The fiducials can be identified using X-rays without etching away portions of the innerlayer panel to expose the fiducials.

Abstract translation: 内层板在制造过程中提供高密度基准。 可以使用X射线识别基准，而不蚀刻掉内层面板的部分以暴露基准。

公开(公告)号：US07382627B2

公开(公告)日：2008-06-03

申请号：US10967781

申请日：2004-10-18

Applicant: William J. Borland ,  G. Sidney Cox ,  David Ross McGregor

Inventor： William J. Borland ,  G. Sidney Cox ,  David Ross McGregor

IPC: H05K1/18

CPC classification number: H01C17/06533 ,  H01C7/005 ,  H01C17/06586 ,  H01G4/40 ,  H05K1/162 ,  H05K1/167 ,  H05K3/429 ,  H05K2201/0209 ,  H05K2201/09309 ,  H05K2201/09763 ,  Y10T29/49155

Abstract: A capacitive/resistive device provides both resistive and capacitive functions. The capacitive/resistive device may be embedded within a layer of a printed wiring board. Embedding the capacitive/resistive device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability. Conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability.

Abstract translation: 电容/电阻器件提供电阻和电容功能。 电容/电阻装置可以嵌入印刷电路板的层内。 嵌入电容/电阻器件节省了电路板表面的空间，并减少了焊接连接的数量，从而提高了可靠性。 节省板表面积，减少焊接数量，提高可靠性。

公开(公告)号：US07072167B2

公开(公告)日：2006-07-04

申请号：US10878877

申请日：2004-06-28

Applicant: William J. Borland

Inventor： William J. Borland

IPC: H01G4/005

CPC classification number: H01G4/01 ,  H05K1/092 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/09763 ,  Y10T29/4913

Abstract: A capacitor structure is fabricated by forming a pattern of first dielectrics over a foil, forming first electrodes over the first dielectrics, and co-firing the first dielectrics and the first electrodes. Co-firing of the dielectrics and the electrodes alleviates cracking caused by differences in thermal coefficient of expansion (TCE) between the electrodes and the dielectrics. Co-firing also ensures a strong bond between the dielectrics and the electrodes. In addition, co-firing allows multi-layer capacitor structures to be constructed, and allows the capacitor electrodes to be formed from copper.

Abstract translation: 通过在箔上形成第一电介质的图案来形成电容器结构，在第一电介质上形成第一电极，并共烧第一电介质和第一电极。 电介质和电极的共烧可减轻由电极和电介质之间的热膨胀系数（TCE）的差异引起的开裂。 共烧也确保电介质和电极之间的牢固结合。 另外，共烧允许构造多层电容器结构，并且允许电容器电极由铜形成。

公开(公告)号：US07688569B2

公开(公告)日：2010-03-30

申请号：US10801257

申请日：2004-03-16

Applicant: William J. Borland ,  Alton Bruce Jones, III ,  Olga L. Renovales ,  Kenneth Warren Hang

Inventor： William J. Borland ,  Alton Bruce Jones, III ,  Olga L. Renovales ,  Kenneth Warren Hang

IPC: H01G4/06

CPC classification number: C04B35/468 ,  C04B2235/445 ,  C04B2235/6562 ,  H01G4/008 ,  H01G4/1227 ,  H01G4/33 ,  H05K1/162 ,  H05K3/1291 ,  H05K2201/017 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/1126

Abstract: Dielectric powder and thick-film paste compositions are formed having high dielectric constants, low loss tangents, and other desirable electrical and physical properties. Conductive powder and paste compositions are formed having desirable electrical and physical properties. The dielectric powder and thick-film paste compositions can be used in combination with the conductive powder and paste compositions to form capacitors and other fired-on-foil passive circuit components.

Abstract translation: 形成介电粉末和厚膜糊组合物，其具有高介电常数，低损耗切线和其它所需的电学和物理性能。 形成具有所需电学和物理性质的导电粉末和糊剂组合物。 电介质粉末和厚膜糊剂组合物可以与导电粉末和糊剂组合物组合使用，以形成电容器和其它无卤电路元件。

公开(公告)号：US20100073845A1

公开(公告)日：2010-03-25

申请号：US12237409

申请日：2008-09-25

Applicant: SEIGI SUH ,  Esther Kim ,  William J. Borland ,  Christopher Allen Gross ,  Omega N. Mack ,  Timothy R. Overcash

Inventor： SEIGI SUH ,  Esther Kim ,  William J. Borland ,  Christopher Allen Gross ,  Omega N. Mack ,  Timothy R. Overcash

IPC: H01G4/00 ,  B05D5/12

CPC classification number: H01G4/12 ,  H01G13/00 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2203/1126 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49163

Abstract: Disclosed are methods of making a dielectric on a metal foil, and a method of making a large area capacitor that includes a dielectric on a metal foil. A first dielectric layer is formed over the metal foil by physical vapor deposition, and a dielectric precursor layer is formed over the first dielectric layer by chemical solution deposition. The metal foil, first dielectric layer and dielectric precursor layer are prefired at a prefiring temperature in the range of 350 to 650° C. The prefired dielectric precursor layer, the first dielectric layer and the base metal foil are subsequently fired at a firing temperature in the range of 700 to 1200° C.

Abstract translation: 公开了在金属箔上制造电介质的方法，以及制造在金属箔上包含电介质的大面积电容器的方法。 通过物理气相沉积在金属箔上形成第一电介质层，并且通过化学溶液沉积在第一介电层上形成电介质前体层。 金属箔，第一电介质层和电介质前体层在预热温度为350至650℃的范围内预烧制。预烧电介质前体层，第一介电层和贱金属箔随后在焙烧温度 范围700〜1200℃