公开(公告)号：US20240354110A1

公开(公告)日：2024-10-24

申请号：US18639815

申请日：2024-04-18

申请人： Ampere Computing LLC

发明人： Erika Susana ALCORTA LOZANO ,  Mahesh Jagdish MADHAV ,  Raymond Scott TETRICK

IPC分类号： G06F9/38 ,  G06F12/0875

CPC分类号： G06F9/3802 ,  G06F12/0875 ,  G06F2212/452

摘要： Disclosed are techniques for runtime adaptive prefetching in a many-core system. In an aspect, a method for runtime adaptive prefetching in a many-core system may include periodically performing the following steps: determining, for a first processor core in a many-core system, a workload classification based on at least one performance indicator of the first processor core; determining a first prefetching configuration from a plurality of prefetching configurations based on the workload classification; and configuring at least the first processor core according to the first prefetching configuration.

公开(公告)号：US20240005004A1

公开(公告)日：2024-01-04

申请号：US17809889

申请日：2022-06-29

申请人： Ampere Computing LLC

发明人： Harb ABDULHAMID ,  Scott WALTON ,  Kha NGUYEN

IPC分类号： G06F21/57 ,  G06F8/65

CPC分类号： G06F21/572 ,  G06F21/575 ,  G06F8/66 ,  G06F2221/033

摘要： A system and method are provided that enable a processor to have the immutable code and data that it uses for its boot process to be securely patched. A system may include a read only memory (ROM) storing one or more certificates and instructions, an array of one-time programmable (OTP) indicators, a bootstrap controller connected to the ROM and the array of OTP indicators, and a random access memory (RAM) connected to the bootstrap controller. The bootstrap controller is configured to verify integrity of firmware for boot based on certificates stored in ROM, check for a patch in the array of OTP indicators, and write the one or more certificates and the instructions in ROM and the patch into the RAM. The patch may be loaded into RAM by the bootstrap controller and overwrite ROM instructions or certificates in RAM.

公开(公告)号：US20240005003A1

公开(公告)日：2024-01-04

申请号：US17809888

申请日：2022-06-29

申请人： Ampere Computing LLC

发明人： Sachhidh KANNAN ,  Shivnandan KAUSHIK ,  Harb ABDULHAMID ,  Yogesh BANSAL ,  Vanshidhar KONDA

IPC分类号： G06F21/57

CPC分类号： G06F21/572

摘要： Disclosed are techniques for performing a low-impact firmware update to a first microcontroller. In an aspect, a security entity communicatively coupled to the first microcontroller receives an update to firmware of the first microcontroller, authenticates the update to the firmware of the first microcontroller to prevent a security-related rollback, offloads system management tasks and interrupt handling from the first microcontroller to at least a second microcontroller communicatively coupled to the first microcontroller, coordinates installation of the update to the firmware of the first microcontroller without taking processing cycles from host software, and restores, to the first microcontroller, system management states occurring after the system management tasks and interrupt handling are offloaded from the first microcontroller.

公开(公告)号：US20240004792A1

公开(公告)日：2024-01-04

申请号：US17809886

申请日：2022-06-29

申请人： Ampere Computing LLC

发明人： Rahul NADKARNI

IPC分类号： G06F12/0811

CPC分类号： G06F12/0811 ,  G06F2212/1024

摘要： A memory with data array (e.g., L2 cache) addressable in rows and columns and techniques to access data therein are proposed. Unlike conventional data arrays, the proposed memory allows data access to be initiated based on a row (or set) address even though the column (or way) address is not yet available. When the column address is determined, it can be used to select the correct data. Since the data access is started prior to determining the column address, memory access latency is reduced.

公开(公告)号：US20230418620A1

公开(公告)日：2023-12-28

申请号：US17808946

申请日：2022-06-24

申请人： Ampere Computing LLC

发明人： Kha Hong Nguyen ,  Harb Ali Abdulhamid

IPC分类号： G06F9/4401

CPC分类号： G06F9/4405

摘要： Generalized boot operations for disaggregated, multiple (multi-) semiconductor die (“die”) computing system, and related methods and computer-readable media are disclosed. In exemplary aspects, to provide for generalized boot-up firmware/software for the computing system that does not have to be reconfigured for different configurations of dies in variations of IC packages, a CPU die (or other die) designated as a primary die is configured to perform a discoverable boot process over a side-band discovery bus to discover the other dies present in an IC package of the computing system and to then control their boot-up operations. In this manner, the boot-up firmware/software executed by the primary die to boot-up the computing system can be generalized irrespective of the number of dies and their particular configuration. In this manner, a generalized boot-up firmware/software can be provided to control boot-up operations of the computing system independent of specific dies included.

公开(公告)号：US20230315571A1

公开(公告)日：2023-10-05

申请号：US17707636

申请日：2022-03-29

申请人： Ampere Computing LLC

发明人： Massimo Sutera ,  Nagi Aboulenein ,  Sandeep Brahmadathan

IPC分类号： G06F11/10 ,  G06F12/02

CPC分类号： G06F11/108 ,  G06F12/0246

摘要： A codeword read from memory includes data blocks including data and supplemental blocks including error correction code (ECC) symbols for detecting and correcting data errors. Metadata can be stored in the supplemental blocks to increase memory utilization but using bits of the supplemental blocks for metadata leaves too few bits remaining for the ECC symbols. To maintain error protection, the supplemental blocks include ECC symbols to protect a first data portion of the codeword and parity bits configured to protect a second data portion of the codeword. Errors in the first data portion can be located and corrected using the ECC symbols. Errors in the second data portion can be detected by the parity. For example, the first data portion is encoded based on the second data portion, so locations of parity errors correspond to locations of symbol errors, and parity errors can be corrected.

公开(公告)号：US20230176749A1

公开(公告)日：2023-06-08

申请号：US17963803

申请日：2022-10-11

申请人： Ampere Computing LLC

发明人： Sebastien Hily ,  Nagi Aboulenein ,  Matthew Robert Erler ,  Shivnandan Kaushik ,  Donald Scott Phillips

IPC分类号： G06F3/06

CPC分类号： G06F3/0619 ,  G06F3/0659 ,  G06F3/0673

摘要： Address range memory mirroring in a computer system, and related methods and computer-readable media. The computer system includes one or more memory mirror agents that are each configured to be programmed to mirror write data of a write request to a memory address mapped to the memory mirror agent. The memory mirror agent is configured to mirror write data to a redundant memory space in memory if the write memory address is within a programmed memory space to be mirrored by the memory mirror agent. The memory mirror agent can be programmed to perform memory mirroring based on specific address ranges to provide flexibility in controlling and changing the exact memory space of the memory system to be mirrored. If an error is detected in read data in response to a memory read request, the memory mirror agent can retrieve the stored redundant data to maintain data integrity.

公开(公告)号：US20230083979A1

公开(公告)日：2023-03-16

申请号：US17472259

申请日：2021-09-10

申请人： Ampere Computing LLC

发明人： Phil MITCHELL ,  Harb ABDULHAMID ,  Kha NGUYEN

IPC分类号： G06F21/57 ,  G06F21/54 ,  G06F21/79 ,  G06Q10/08

摘要： A system and method is provided that enables a processor to undergo RMA after being in a secured operating state, where the secure state includes hardware disabling of test access ports and debug ports during a boot process. The apparatus providing this computer security at power-on or boot-up may have at least two one-time programmable indicators, a bootstrap controller that controls at least two boot-time switches and reads the one-time programmable indicators, and a read only memory storing at least one instruction. The bootstrap controller calculates an operating state such as a secure state or RMA state based on the at least two one-time programmable indicators. The bootstrap controller then enables or disables an execution of the at least one instruction or enables or disables a hardware port based on the operating state. The bootstrap controller may provide switching between RMA and secure states via sequential one-time programming of indicators.

公开(公告)号：US20220197807A1

公开(公告)日：2022-06-23

申请号：US17125770

申请日：2020-12-17

申请人： Ampere Computing LLC

发明人： Jonathan Christopher Perry ,  Stephan Jean Jourdan ,  Mahesh Jagdish Madhav ,  Aarti Chandrashekhar

IPC分类号： G06F12/0862 ,  G06F12/128 ,  G06F12/02 ,  G06F13/16

摘要： An apparatus configured to provide latency-aware prefetching, and related systems, methods, and computer-readable media, are disclosed. The apparatus comprises a prefetch buffer comprising at least a first entry, and the first entry comprises a memory operation prefetch request portion storing a first previous memory operation prefetch request. The apparatus further comprises a prefetch buffer replacement circuit, which is configured to select an entry of the prefetch buffer storing a previous memory operation prefetch request for replacement with a subsequent memory operation prefetch request, and to replace the previous memory operation prefetch request in the selected entry with the subsequent memory operation prefetch request.

公开(公告)号：US20220091997A1

公开(公告)日：2022-03-24

申请号：US17457081

申请日：2021-12-01

申请人： Ampere Computing LLC

发明人： George Van Horn Leming, III ,  John Gregory Favor ,  Stephan Jean Jourdan ,  Jonathan Christopher Perry ,  Bret Leslie Toll

IPC分类号： G06F12/1027

摘要： A memory management unit (MMU) including a unified translation lookaside buffer (TLB) supporting a plurality of page sizes is disclosed. In one aspect, the MMU is further configured to store and dynamically update page size residency metadata associated with each of the plurality of page sizes. The page size residency metadata may include most recently used (MRU) page size data and/or a counter for each page size indicating how many pages of that page size are resident in the unified TLB. The unified TLB is configured to determine an order in which to perform a TLB lookup for at least a subset of page sizes of the plurality of page sizes based on the page size residency metadata