公开(公告)号：US20210191877A1

公开(公告)日：2021-06-24

申请号：US16722974

申请日：2019-12-20

申请人： Ampere Computing LLC

发明人： George Van Horn Leming, III ,  John Gregory Favor ,  Stephan Jean Jourdan ,  Jonathan Christopher Perry ,  Bret Leslie Toll

IPC分类号： G06F12/1027

摘要： A memory management unit (MMU) including a unified translation lookaside buffer (TLB) supporting a plurality of page sizes is disclosed. In one aspect, the MMU is further configured to store and dynamically update page size residency metadata associated with each of the plurality of page sizes. The page size residency metadata may include most recently used (MRU) page size data and/or a counter for each page size indicating how many pages of that page size are resident in the unified TLB. The unified TLB is configured to determine an order in which to perform a TLB lookup for at least a subset of page sizes of the plurality of page sizes based on the page size residency metadata

公开(公告)号：US20220091997A1

公开(公告)日：2022-03-24

申请号：US17457081

申请日：2021-12-01

申请人： Ampere Computing LLC

发明人： George Van Horn Leming, III ,  John Gregory Favor ,  Stephan Jean Jourdan ,  Jonathan Christopher Perry ,  Bret Leslie Toll

IPC分类号： G06F12/1027

摘要： A memory management unit (MMU) including a unified translation lookaside buffer (TLB) supporting a plurality of page sizes is disclosed. In one aspect, the MMU is further configured to store and dynamically update page size residency metadata associated with each of the plurality of page sizes. The page size residency metadata may include most recently used (MRU) page size data and/or a counter for each page size indicating how many pages of that page size are resident in the unified TLB. The unified TLB is configured to determine an order in which to perform a TLB lookup for at least a subset of page sizes of the plurality of page sizes based on the page size residency metadata

公开(公告)号：US11586537B2

公开(公告)日：2023-02-21

申请号：US17393715

申请日：2021-08-04

申请人： Ampere Computing LLC

发明人： Benjamin Crawford Chaffin ,  Bret Leslie Toll ,  Jonathan Christopher Perry ,  Nagi Aboulenein

IPC分类号： G06F12/00 ,  G06F12/0802

摘要： A data processing system includes a store datapath configured to perform tag checking in a store operation to a store address associated with a cache line in a memory. The store datapath includes a cache lookup circuit configured to pre-load a store cache line that is to be updated in the store operation, wherein the store cache line comprises the cache line in the memory to be updated in the store operation. The store datapath also includes a tag check circuit configured to compare a store address tag associated with the store address to a store operation tag associated with the store operation. The data processing system may include a load datapath configured to perform tag checking in a load operation from a load cache line in the memory by comparing a load address tag associated with the load address to a load operation tag associated with the load operation.

公开(公告)号：US11822487B2

公开(公告)日：2023-11-21

申请号：US17457081

申请日：2021-12-01

申请人： Ampere Computing LLC

发明人： George Van Horn Leming, III ,  John Gregory Favor ,  Stephan Jean Jourdan ,  Jonathan Christopher Perry ,  Bret Leslie Toll

IPC分类号： G06F12/1027

CPC分类号： G06F12/1027 ,  G06F2212/68

摘要： A memory management unit (MMU) including a unified translation lookaside buffer (TLB) supporting a plurality of page sizes is disclosed. In one aspect, the MMU is further configured to store and dynamically update page size residency metadata associated with each of the plurality of page sizes. The page size residency metadata may include most recently used (MRU) page size data and/or a counter for each page size indicating how many pages of that page size are resident in the unified TLB. The unified TLB is configured to determine an order in which to perform a TLB lookup for at least a subset of page sizes of the plurality of page sizes based on the page size residency metadata.

公开(公告)号：US11386016B2

公开(公告)日：2022-07-12

申请号：US16722974

申请日：2019-12-20

申请人： Ampere Computing LLC

发明人： George Van Horn Leming, III ,  John Gregory Favor ,  Stephan Jean Jourdan ,  Jonathan Christopher Perry ,  Bret Leslie Toll

IPC分类号： G06F12/1027

摘要： A memory management unit (MMU) including a unified translation lookaside buffer (TLB) supporting a plurality of page sizes is disclosed. In one aspect, the MMU is further configured to store and dynamically update page size residency metadata associated with each of the plurality of page sizes. The page size residency metadata may include most recently used (MRU) page size data and/or a counter for each page size indicating how many pages of that page size are resident in the unified TLB. The unified TLB is configured to determine an order in which to perform a TLB lookup for at least a subset of page sizes of the plurality of page sizes based on the page size residency metadata.

公开(公告)号：US20220004501A1

公开(公告)日：2022-01-06

申请号：US16919171

申请日：2020-07-02

申请人： Ampere Computing LLC

发明人： John Gregory Favor ,  Stephan Jean Jourdan ,  Jonathan Christopher Perry ,  Kjeld Svendsen ,  Bret Leslie Toll

IPC分类号： G06F12/1045

摘要： An apparatus configured to provide just-in-time synonym handling, and related systems, methods, and computer-readable media, are disclosed. The apparatus includes a first cache comprising a translation lookaside buffer (TLB) and a hit/miss block. The first cache is configured to form a miss request associated with an access to the first cache and provide the miss request to a second cache. The miss request comprises a physical address provided by the TLB and miss information provided by the hit/miss block. The first cache is further configured to receive, from the second cache, previously-stored metadata associated with an entry in the second cache. The entry in the second cache is associated with the miss request. The first cache may further include a synonym detection block, which is configured to identify a cache line in the first cache for invalidation based on the previously-stored metadata received from the second cache