公开(公告)号：US06440818B1

公开(公告)日：2002-08-27

申请号：US09828789

申请日：2001-04-10

申请人： Yuan-Li Tsai ,  Kuo-Hua Ho ,  Kai-Jen Ko ,  Cheng-Hui Chung

发明人： Yuan-Li Tsai ,  Kuo-Hua Ho ,  Kai-Jen Ko ,  Cheng-Hui Chung

IPC分类号： H01L2176

CPC分类号： H01L21/76202 ,  H01L21/31111 ,  H01L21/31116

摘要： A semiconductor wafer includes a silicon substrate, an active area positioned on the silicon substrate, and a field oxide layer positioned on the surface of the silicon substrate surrounding the active area. The present invention forms a doped area in the silicon substrate and within the active area and then deposits a dielectric layer on the surface of the semiconductor wafer. A dry etching process is performed to remove the dielectric layer. The top power of the dry etching process ranges between three hundred and five hundred watts to prevent damage to the silicon substrate near the field oxide layer and within the active area by the dry etching process, and to reduce the leakage current of the doped area. Additionally, the present invention also uses a wet etching process to remove the dielectric layer, which prevents an anisotropic physical impact on the silicon substrate near the field oxide layer to reduce the leakage current of the doped area.

摘要翻译： 半导体晶片包括硅衬底，位于硅衬底上的有源区域和位于围绕有源区域的硅衬底表面上的场氧化物层。 本发明在硅​​衬底中并在有源区内形成掺杂区，然后在半导体晶片的表面上沉积介电层。 进行干蚀刻处理以去除电介质层。 干蚀刻工艺的最大功率范围在三百五百瓦特之间，以防止通过干蚀刻工艺在场氧化物层附近和有源区域内的硅衬底损坏，并减少掺杂区域的漏电流。 此外，本发明还使用湿式蚀刻工艺来去除电介质层，这防止了在场氧化物层附近的硅衬底上的各向异性物理冲击以减少掺杂区域的漏电流。

公开(公告)号：US5668031A

公开(公告)日：1997-09-16

申请号：US658673

申请日：1996-06-04

申请人： Chen-Chiu Hsue ,  Cheng-Hui Chung ,  Yi-Chung Sheng

发明人： Chen-Chiu Hsue ,  Cheng-Hui Chung ,  Yi-Chung Sheng

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L21/70

CPC分类号： H01L27/11253 ,  H01L27/112

摘要： A method of fabricating a high density flat mask read only memory. At first a plurality of trenches are formed in a surface of a silicon substrate at predetermined desired source-drain electrodes areas. A dielectric layer is formed on at least the surface of the trenches. A first polysilicon layer is formed over the dielectric layer and then portions of the first polysilicon layer are removed to leave a portion thereof on the bottom of each trench. Using the first polysilicon layer as an etch stop layer, the dielectric layer is etched. A second polysilicon layer then is formed on the surface of the silicon substrate, the first polysilicon layer and the dielectric layer, and then the the second polysilicon layer is etched back to the substrate surface to form the source-drain electrode areas, that is, the bit lines. On the surface of the bit lines and the silicon substrate, a gate oxide layer and a third polysilicon layer are formed sequentially. Finally, the gate oxide layer and the third polysilicon layer are defined to form gate electrodes, that is, word lines for the memory.

摘要翻译： 一种制造高密度平面掩模只读存储器的方法。 首先，在预定的期望的源极 - 漏极电极区域的硅衬底的表面中形成多个沟槽。 在沟槽的至少表面上形成介电层。 在电介质层上形成第一多晶硅层，然后去除第一多晶硅层的部分，以将其部分留在每个沟槽的底部。 使用第一多晶硅层作为蚀刻停止层，蚀刻介电层。 然后在硅衬底，第一多晶硅层和电介质层的表面上形成第二多晶硅层，然后将第二多晶硅层回蚀刻到衬底表面以形成源极 - 漏极电极区域，即， 位线。 在位线和硅衬底的表面上依次形成栅氧化层和第三多晶硅层。 最后，栅极氧化物层和第三多晶硅层被定义为形成栅电极，即用于存储器的字线。

公开(公告)号：US06242315B1

公开(公告)日：2001-06-05

申请号：US09186126

申请日：1998-11-04

申请人： Chen-Bin Lin ,  Cheng-Hui Chung ,  Yei-Hsiung Lin ,  Ching-Chun Huang

发明人： Chen-Bin Lin ,  Cheng-Hui Chung ,  Yei-Hsiung Lin ,  Ching-Chun Huang

IPC分类号： H01L2120

CPC分类号： H01L28/55 ,  H01L21/76838 ,  H01L28/60

摘要： A method of manufacturing the metallic electrodes of a capacitor in a mixed mode semiconductor device. The method comprises the steps of providing a substrate having a conductive layer and the lower electrode of a capacitor formed thereon, and then depositing a dielectric layer over the substrate. A first opening and a second opening are then formed in the dielectric layer. The first opening exposes a portion of the conductive layer while the second opening exposes a portion of the lower electrode. Finally, a conductive plug and the upper electrode of the capacitor are formed in the respective first and second openings that are in corresponding positions above the conductive layer and lower electrode, respectively.

摘要翻译： 一种在混合模式半导体器件中制造电容器的金属电极的方法。 该方法包括以下步骤：提供具有导电层和形成在其上的电容器的下电极的衬底，然后在衬底上沉积介电层。 然后在电介质层中形成第一开口和第二开口。 第一开口暴露导电层的一部分，而第二开口暴露下部电极的一部分。 最后，分别在导电层和下电极上方的相应位置的相应的第一和第二开口中形成导电插塞和电容器的上电极。

公开(公告)号：US6086951A

公开(公告)日：2000-07-11

申请号：US332342

申请日：1999-06-14

申请人： Chen-Bin Lin ,  Cheng-Hui Chung ,  Yu-Ju Liu

发明人： Chen-Bin Lin ,  Cheng-Hui Chung ,  Yu-Ju Liu

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L28/55 ,  H01L28/60 ,  H01L21/76801 ,  H01L21/76838

摘要： A method of forming metallic capacitor. The method includes forming a lower electrode for forming the capacitor and a metal conductive line over an inter-layer dielectric such that there are gaps between and on the sides of the lower electrode and the metal conductive line. Thereafter, a first oxide layer is formed that fills the gap, and then a second oxide layer is formed over the inter-layer dielectric. The second oxide layer is later patterned to form a cap oxide layer having an opening that exposes a portion of the lower electrode. Subsequently, a thin dielectric layer is formed over the lower electrode and the cap oxide layer. Finally, an upper electrode is formed over the thin dielectric layer filling the opening.

摘要翻译： 一种形成金属电容器的方法。 该方法包括形成用于形成电容器的下电极和在层间电介质上的金属导电线，使得在下电极和金属导线之间的两侧之间和之间存在间隙。 此后，形成填充间隙的第一氧化物层，然后在层间电介质上形成第二氧化物层。 随后将第二氧化物层图案化以形成具有暴露下部电极的一部分的开口的帽氧化物层。 随后，在下电极和盖氧化物层上形成薄介电层。 最后，在填充开口的薄介电层上形成上电极。

公开(公告)号：US06355530B1

公开(公告)日：2002-03-12

申请号：US09630867

申请日：2000-08-02

申请人： James Ho ,  Cheng-Hui Chung ,  Chen-Bin Lin

发明人： James Ho ,  Cheng-Hui Chung ,  Chen-Bin Lin

IPC分类号： H01L218236

CPC分类号： H01L27/1126 ,  H01L27/112

摘要： A method of manufacturing a mask ROM. A sacrificial silicon oxide layer is formed on the active region upon the substrate. Patterning the sacrificial silicon oxide layer in order to form a plurality of parallel openings, thereby exposing a portion of the active region. A polysilicon layer is formed on the openings and openings are formed thereon. An ion implantation process is performed on the polysilicon layer. Using a thermal flow process, the ions within the polysilicon layer are driven through the openings into the lower portion of the substrate, thereby forming an ion doping region. The polysilicon layer is etchbacked until the sacrificial silicon oxide layer is exposed. The sacrificial silicon oxide layer is removed.

摘要翻译： 一种制造掩模ROM的方法。 在衬底上的有源区上形成牺牲氧化硅层。 对牺牲氧化硅层进行成形以便形成多个平行的开口，从而暴露一部分有源区。 在开口上形成多晶硅层，在其上形成开口。 在多晶硅层上进行离子注入工艺。 使用热流程，多晶硅层内的离子通过开口被驱动到衬底的下部，从而形成离子掺杂区域。 蚀刻多晶硅层直到牺牲氧化硅层露出。 去除牺牲氧化硅层。

公开(公告)号：US06277729B1

公开(公告)日：2001-08-21

申请号：US09042855

申请日：1998-03-17

申请人： Bing-Chang Wu ,  Cheng-Hui Chung

发明人： Bing-Chang Wu ,  Cheng-Hui Chung

IPC分类号： H01L214763

CPC分类号： H01L21/76856 ,  H01L21/76843

摘要： A method for improving the fabrication of a transistor barrier layer that utilizes an ion bombardment treatment after the formation of the titanium nitride layer for reducing contact resistance and preventing tungsten plug stringer generation. The method comprises the step of patterning a transistor to form vias, and then depositing a titanium/titanium nitride layer over the transistor surface using a collimator sputtering method. Next, an ion bombardment treatment is carried out, and then a rapid thermal processing operation is performed. Finally, tungsten is deposited to fill the vias follow by a planarization. This invention is able to lower contact resistance because titanium in the titanium layer will not react with gaseous ammonia or nitrogen in the reacting chamber to form a high resistance titanium nitride layer during rapid thermal processing operation. In the meantime, no short-circuiting stringers leading from the tungsten plug to the titanium nitride layer below are formed because no cracks are formed in a titanium nitride layer that has been subjected to a stress reducing ion bombardment treatment.

摘要翻译： 一种用于改善在形成用于降低接触电阻并防止钨插塞纵梁产生的氮化钛层形成之后利用离子轰击处理的晶体管势垒层的制造方法。 该方法包括图案化晶体管以形成通孔，然后使用准直器溅射方法在晶体管表面上沉积钛/氮化钛层的步骤。 接下来，进行离子轰击处理，然后进行快速热处理操作。 最后，通过平坦化沉积钨来填充通孔。 本发明能够降低接触电阻，因为在快速热处理操作期间，钛层中的钛不会与反应室中的气态氨或氮反应形成高电阻氮化钛层。 同时，由于在经过减压离子轰击处理的氮化钛层中没有形成裂纹，因此形成了从钨丝塞向下方的氮化钛层的短路桁条。

公开(公告)号：US5846865A

公开(公告)日：1998-12-08

申请号：US745468

申请日：1996-11-12

申请人： Yi-Chung Sheng ,  Cheng-Hui Chung ,  Jih-Wen Chou

发明人： Yi-Chung Sheng ,  Cheng-Hui Chung ,  Jih-Wen Chou

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L21/8236

CPC分类号： H01L27/11253 ,  H01L27/112 ,  Y10S148/02

摘要： A method of fabricating flat-cell mask ROM devices having buried bit-lines that will not be subject to punch-through between neighboring bit lines as a result of heating in subsequent steps after the buried bit-lines are formed. In the method, the first step is to prepare a semiconductor substrate with a gate oxide layer formed thereon. Thereafter, a first polysilicon layer is formed over the gate oxide layer, and a plurality of trenches at predetermined positions, with these trenches extending through the gate oxide and first polysilicon layer and into the substrate to a predetermined depth. Then, trenches are filled with tungsten to form a plurality of source/drain regions. A second polysilicon layer is then formed over the first polysilicon layer, and an insulating layers is formed over each of the source/drain regions. Thereafter, a third polysilicon layer is formed over the second polysilicon layer and the insulating layers, and finally the third polysilicon layer is defined to form a gate for the integrated circuit device. Since the source/drain regions are made of tungsten metal, the spacing distance therebetween will not be changed when subjected to high-temperature conditions during subsequent process steps. The punch-through effect can thus be avoided.

摘要翻译： 一种制造平面单元掩膜ROM器件的方法，其具有在形成掩埋位线之后的随后步骤中加热的结果之后不会在相邻位线之间穿透的掩埋位线。 在该方法中，第一步是制备其上形成有栅氧化层的半导体衬底。 此后，在栅极氧化物层上形成第一多晶硅层，并在预定位置形成多个沟槽，其中这些沟槽延伸穿过栅极氧化物和第一多晶硅层并进入衬底至预定深度。 然后，用钨填充沟槽以形成多个源极/漏极区域。 然后在第一多晶硅层上形成第二多晶硅层，并且在每个源/漏区上形成绝缘层。 此后，在第二多晶硅层和绝缘层上形成第三多晶硅层，最后形成第三多晶硅层以形成用于集成电路器件的栅极。 由于源极/漏极区域由钨金属制成，因此在后续工艺步骤中经受高温条件时，它们之间的间隔距离将不会改变。 因此可以避免穿透效果。

公开(公告)号：US20050020061A1

公开(公告)日：2005-01-27

申请号：US10622690

申请日：2003-07-21

申请人： Jui-Hua Fang ,  Cheng-Hui Chung ,  Chia-Hui Lu

发明人： Jui-Hua Fang ,  Cheng-Hui Chung ,  Chia-Hui Lu

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/7685 ,  H01L21/76838

摘要： A method of modifying a conductive wiring. First, a semiconductor substrate is provided. Next, a first barrier is formed on the semiconductor. A conductive wiring is formed on the first barrier. A second barrier is formed on the conductive wiring. Finally, a thermal treatment is performed on the semiconductor substrate.

摘要翻译： 一种修改导电布线的方法。 首先，提供半导体基板。 接下来，在半导体上形成第一屏障。 导电布线形成在第一屏障上。 在导电布线上形成第二屏障。 最后，对半导体衬底进行热处理。

公开(公告)号：US06225209B1

公开(公告)日：2001-05-01

申请号：US09150525

申请日：1998-09-10

申请人： Yei-Hsiung Lin ,  Chih-Chun Huang ,  Chen-Bin Lin ,  Cheng-Hui Chung

发明人： Yei-Hsiung Lin ,  Chih-Chun Huang ,  Chen-Bin Lin ,  Cheng-Hui Chung

IPC分类号： H01L214763

CPC分类号： H01L21/02126 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/31625 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/823425 ,  H01L21/823475 ,  H01L29/665

摘要： A method for fabricating a crack resistant inter-layer dielectric for a salicide process. The method includes forming an insulating layer on a provided substrate, forming a planarized inter-layer dielectric layer on the insulating layer, and performing a short-duration thermal treatment to increase the density of the inter-layer dielectric layer.

摘要翻译： 一种用于制造用于自对准硅化物工艺的耐裂纹层间电介质的方法。 该方法包括在所提供的衬底上形成绝缘层，在绝缘层上形成平坦化的层间电介质层，并进行短时间热处理以增加层间电介质层的密度。

公开(公告)号：US5891779A

公开(公告)日：1999-04-06

申请号：US9300

申请日：1998-01-20

申请人： Cheng-Hui Chung ,  Yi-Chung Sheng

发明人： Cheng-Hui Chung ,  Yi-Chung Sheng

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L21/8236

CPC分类号： H01L27/1128 ,  H01L27/112

摘要： A method of fabricating a tetra-state mask read only memory. A memory device is fabricated. Using a first photo-resist to dope the channel regions, a first coding step is performed to obtain a transistor having two different threshold voltage. Covering a gate oxide layer, and etching the first photo-resist layer to form a via, a buried bit line is formed. A poly-silicon layer is formed on the gate oxide layer. Doping the second poly-silicon layer by implanting ions to the source/drain regions, and using a second photo-resist layer, a second coding step is performed. An inverse transistor with two different threshold voltage is formed.

摘要翻译： 制造四态掩模只读存储器的方法。 制造存储器件。 使用第一光致抗蚀剂来掺杂沟道区，执行第一编码步骤以获得具有两个不同阈值电压的晶体管。 覆盖栅极氧化物层，蚀刻第一光致抗蚀剂层以形成通孔，形成掩埋位线。 在栅氧化层上形成多晶硅层。 通过将离子注入到源极/漏极区域来掺杂第二多晶硅层，并且使用第二光致抗蚀剂层，执行第二编码步骤。 形成具有两个不同阈值电压的反相晶体管。