公开(公告)号：US06797983B2

公开(公告)日：2004-09-28

申请号：US10060460

申请日：2002-01-30

申请人： Ralph Chen ,  Marcus Yang ,  Yuan-Li Tsai ,  Ching-Chun Huang ,  Sheng-Hsiung Yang

发明人： Ralph Chen ,  Marcus Yang ,  Yuan-Li Tsai ,  Ching-Chun Huang ,  Sheng-Hsiung Yang

IPC分类号： H01L2100

CPC分类号： G02F1/136277

摘要： A method is provided to fabricate a LCOS back plane structure. The present invention utilized a HV device such as HV CMOS transistor (high voltage complementary metal oxide semiconductor transistor) and a HV capacitor layer are applied to the substrate. Furthermore, the HV capacitor layer has a higher dielectric layer and coupling ratio to sustain the higher operating voltage, such that the operating capacitance can be raised. Moreover, the HV CMOS transistor is combined with a mirror layer which has a higher reflective property, such that the LCOS back-plate structure has the better contrast and chrominance output in per area unit, when the operating voltage range is increased.

摘要翻译： 提供了一种制造LCOS背板结构的方法。 本发明将HV HV晶体管（高电压互补金属氧化物半导体晶体管）和HV电容层用于HV基板。 此外，HV电容层具有更高的介电层和耦合比，以维持更高的工作电压，使得可以提高工作电容。 此外，HV CMOS晶体管与具有较高反射特性的镜面层组合，使得当工作电压范围增加时，LCOS背板结构在每单位面积具有更好的对比度和色度输出。

公开(公告)号：US06624079B2

公开(公告)日：2003-09-23

申请号：US09931953

申请日：2001-08-20

申请人： Yuan-Li Tsai ,  Marcus Yang ,  Ralph Chen ,  Heng-Chun Kao ,  Ching-Chun Hwang

发明人： Yuan-Li Tsai ,  Marcus Yang ,  Ralph Chen ,  Heng-Chun Kao ,  Ching-Chun Hwang

IPC分类号： H01L21311

CPC分类号： H01L28/20 ,  H01L27/0676 ,  H01L27/0802 ,  H01L27/0805

摘要： The method for forming high voltage device combined with a mixed mode process use an un-doped polysilicon layer instead of the conventional polysilicon layer. In the high resistance area, the ion implant is not used until the source region and the drain region are formed. A resistor is formed by etching oxide-nitride-oxide layer and performing ion implant process by using BF2 radical to the un-doped polysilicon layer to control the resistance. Then multitudes of contact are formed, wherein the high dosage of BF2 implant would reduce resistance between contacts and resistor.

摘要翻译： 与混合模式工艺结合的形成高电压器件的方法使用未掺杂多晶硅层而不是常规多晶硅层。 在高电阻区域中，直到形成源极区域和漏极区域才能使用离子注入。 通过蚀刻氧化物 - 氮化物 - 氧化物层并通过使用BF 2自由基对未掺杂的多晶硅层进行离子注入工艺来形成电阻器来控制电阻。 然后形成大量的接触，其中高剂量的BF 2植入物将降低触点和电阻器之间的电阻。

公开(公告)号：US06638841B2

公开(公告)日：2003-10-28

申请号：US10117042

申请日：2002-04-08

申请人： Kai-Jen Ko ,  Yuan-Li Tsai ,  Ming-Hui Wu ,  Steven Huang ,  Ching-Chun Hwang

发明人： Kai-Jen Ko ,  Yuan-Li Tsai ,  Ming-Hui Wu ,  Steven Huang ,  Ching-Chun Hwang

IPC分类号： H01L218238

CPC分类号： H01L21/823842

摘要： A method for reducing a gate length bias is disclosed. The method utilizes an additional blanket ion implantation process to adjust the etching property of the undoped conductive layer. According to the present invention, a polysilicon layer is used to form NMOS and PMOS gate electrodes so that the gate length bias between the NMOS gate electrodes and the PMOS gate electrodes can be effectively reduced.

摘要翻译： 公开了一种减小栅极长度偏置的方法。 该方法利用额外的覆盖层离子注入工艺来调节未掺杂的导电层的蚀刻性能。 根据本发明，使用多晶硅层来形成NMOS和PMOS栅电极，从而可以有效地减小NMOS栅电极和PMOS栅电极之间的栅极长度偏置。

公开(公告)号：US06680258B1

公开(公告)日：2004-01-20

申请号：US10261947

申请日：2002-10-02

申请人： Yuan-Li Tsai ,  Yu-Piao Wang

发明人： Yuan-Li Tsai ,  Yu-Piao Wang

IPC分类号： H01L21302

CPC分类号： H01L21/76802 ,  H01L21/31144 ,  H01L21/3143 ,  H01L21/3185

摘要： An opening through an insulating layer between a first layer and a second layer of a semiconductor device is formed where the second layer is a polysilicon or amorphous silicon hard mask layer. The polysilicon or amorphous silicon hard mask layer is etched to form at least one opening through the polysilicon or amorphous silicon hard mask layer using a patterning layer as a mask having at least one opening. The insulating layer is etched to form the opening through the insulating layer using the etched polysilicon or amorphous silicon hard mask layer as a mask. The etched polysilicon or amorphous silicon hard mask layer is nitridized prior to subsequent processing.

摘要翻译： 形成半导体器件的第一层和第二层之间的绝缘层的开口，其中第二层是多晶硅或非晶硅硬掩模层。 使用图案化层作为具有至少一个开口的掩模，蚀刻多晶硅或非晶硅硬掩模层以形成穿过多晶硅或非晶硅硬掩模层的至少一个开口。 使用蚀刻的多晶硅或非晶硅硬掩模层作为掩模，蚀刻绝缘层以形成穿过绝缘层的开口。 蚀刻的多晶硅或非晶硅硬掩模层在随后的处理之前被氮化。

公开(公告)号：US06440818B1

公开(公告)日：2002-08-27

申请号：US09828789

申请日：2001-04-10

申请人： Yuan-Li Tsai ,  Kuo-Hua Ho ,  Kai-Jen Ko ,  Cheng-Hui Chung

发明人： Yuan-Li Tsai ,  Kuo-Hua Ho ,  Kai-Jen Ko ,  Cheng-Hui Chung

IPC分类号： H01L2176

CPC分类号： H01L21/76202 ,  H01L21/31111 ,  H01L21/31116

摘要： A semiconductor wafer includes a silicon substrate, an active area positioned on the silicon substrate, and a field oxide layer positioned on the surface of the silicon substrate surrounding the active area. The present invention forms a doped area in the silicon substrate and within the active area and then deposits a dielectric layer on the surface of the semiconductor wafer. A dry etching process is performed to remove the dielectric layer. The top power of the dry etching process ranges between three hundred and five hundred watts to prevent damage to the silicon substrate near the field oxide layer and within the active area by the dry etching process, and to reduce the leakage current of the doped area. Additionally, the present invention also uses a wet etching process to remove the dielectric layer, which prevents an anisotropic physical impact on the silicon substrate near the field oxide layer to reduce the leakage current of the doped area.

摘要翻译： 半导体晶片包括硅衬底，位于硅衬底上的有源区域和位于围绕有源区域的硅衬底表面上的场氧化物层。 本发明在硅​​衬底中并在有源区内形成掺杂区，然后在半导体晶片的表面上沉积介电层。 进行干蚀刻处理以去除电介质层。 干蚀刻工艺的最大功率范围在三百五百瓦特之间，以防止通过干蚀刻工艺在场氧化物层附近和有源区域内的硅衬底损坏，并减少掺杂区域的漏电流。 此外，本发明还使用湿式蚀刻工艺来去除电介质层，这防止了在场氧化物层附近的硅衬底上的各向异性物理冲击以减少掺杂区域的漏电流。