公开(公告)号：US20110221070A1

公开(公告)日：2011-09-15

申请号：US13044457

申请日：2011-03-09

申请人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

发明人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L23/49827 ,  H01L21/561 ,  H01L21/76805 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

摘要： According to an embodiment of the invention, a chip package is provided. The chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located in the substrate or under the lower surface thereof, a dielectric layer located between the conducting pads, a hole extending from the upper surface towards the lower surface of the substrate and exposing a portion of the conducting pads, and a conducting layer located in the hole and electrically contacting the conducting pads.

公开(公告)号：US08692382B2

公开(公告)日：2014-04-08

申请号：US13190388

申请日：2011-07-25

申请人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

发明人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC分类号： H01L23/48

CPC分类号： H01L21/76879 ,  B81B7/007 ,  B81B2207/07 ,  B81B2207/092 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/3178 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/13 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/13025 ,  H01L2224/9202 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00

摘要： According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein an upper sidewall of the hole inclines to the lower surface of the substrate, and a lower sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads.

摘要翻译： 根据本发明的实施例，提供了芯片封装。 芯片封装包括：具有上表面和下表面的基板; 位于所述基板的下表面下方的多个导电垫; 位于导电垫之间的电介质层; 从衬底的上表面延伸到下表面的沟槽; 从所述沟槽的底部延伸到所述衬底的下表面的孔，其中所述孔的上侧壁倾斜到所述衬底的下表面，并且所述孔的下侧壁或底部暴露所述导电垫的一部分 ; 以及导电层，其位于所述孔中并电连接到至少一个所述导电焊盘。

公开(公告)号：US08552565B2

公开(公告)日：2013-10-08

申请号：US13204603

申请日：2011-08-05

申请人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

发明人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L21/561 ,  H01L21/76805 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

摘要： A chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located under the lower surface of the substrate, and a dielectric layer located between the conducting pads. A hole is provided in the substrate, which extends from the upper surface towards the lower surface of the substrate. A sidewall or a bottom of the hole exposes a portion of the conducting pads. The upper opening of the hole near the upper surface is smaller than a lower opening of the hole near the lower surface. An upper conducting pad has at least an opening or a trench exposing a lower conducting pad of the conducting pads. A conducting layer is disposed in the hole, which electrically contacting at least one of the conducting pads.

摘要翻译： 芯片封装包括具有上表面和下表面的衬底，位于衬底的下表面下方的多个导电衬垫以及位于导电焊盘之间的电介质层。 在衬底中设置有一个孔，该孔从衬底的上表面向下表面延伸。 孔的侧壁或底部暴露出导电垫的一部分。 上表面附近的孔的上部开口小于靠近下表面的孔的下部开口。 上导电焊盘至少具有暴露导电焊盘的下导电焊盘的开口或沟槽。 导电层设置在孔中，该导电层与至少一个导电垫电接触。

公开(公告)号：US08698316B2

公开(公告)日：2014-04-15

申请号：US13190408

申请日：2011-07-25

申请人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

发明人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC分类号： H01L23/48

CPC分类号： H01L21/76879 ,  B81B7/007 ,  B81B2207/07 ,  B81B2207/092 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L2221/68377 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

摘要： According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein a sidewall of the hole is substantially perpendicular to the lower surface of the substrate, and the sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads.

摘要翻译： 根据本发明的实施例，提供了芯片封装。 芯片封装包括：具有上表面和下表面的基板; 位于所述基板的下表面下方的多个导电焊盘; 位于导电垫之间的电介质层; 从衬底的上表面延伸到下表面的沟槽; 从所述沟槽的底部延伸到所述衬底的下表面的孔，其中所述孔的侧壁基本上垂直于所述衬底的下表面，并且所述孔的侧壁或所述底部露出所述导电垫的一部分 ; 以及导电层，其位于所述孔中并电连接到至少一个所述导电焊盘。

公开(公告)号：US08525345B2

公开(公告)日：2013-09-03

申请号：US13044457

申请日：2011-03-09

申请人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

发明人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L21/561 ,  H01L21/76805 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

摘要： According to an embodiment of the invention, a chip package is provided. The chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located in the substrate or under the lower surface thereof, a dielectric layer located between the conducting pads, a hole extending from the upper surface towards the lower surface of the substrate and exposing a portion of the conducting pads, and a conducting layer located in the hole and electrically contacting the conducting pads.

摘要翻译： 根据本发明的实施例，提供了芯片封装。 芯片封装包括具有上表面和下表面的衬底，位于衬底中或其下表面下方的多个导电焊盘，位于导电焊盘之间的介电层，从上表面向下延伸的孔 表面并暴露一部分导电焊盘，以及导电层，其位于孔中并与导电焊盘电接触。

公开(公告)号：US09559001B2

公开(公告)日：2017-01-31

申请号：US13024156

申请日：2011-02-09

申请人： Yu-Lin Yen ,  Ming-Kun Yang ,  Tsang-Yu Liu ,  Long-Sheng Yeou

发明人： Yu-Lin Yen ,  Ming-Kun Yang ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763 ,  H01L23/58 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L21/76898 ,  H01L21/486 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/05 ,  H01L2224/0501 ,  H01L2224/0557 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/05552

摘要： According to an embodiment of the invention, a chip package is provided, which includes: a substrate having an upper surface and a lower surface; a hole extending from the upper surface toward the lower surface; an insulating layer located overlying a sidewall of the hole; and a material layer located overlying the sidewall of the hole, wherein the material layer is separated from the upper surface of the substrate by a distance and a thickness of the material layer decreases along a direction toward the lower surface.

摘要翻译： 根据本发明的实施例，提供了一种芯片封装，其包括：具有上表面和下表面的基板; 从上表面向下表面延伸的孔; 位于所述孔的侧壁上方的绝缘层; 以及位于所述孔的侧壁上方的材料层，其中所述材料层与所述基板的上表面分离一定距离，并且所述材料层的厚度沿着朝向所述下表面的方向减小。

公开(公告)号：US09024437B2

公开(公告)日：2015-05-05

申请号：US13524985

申请日：2012-06-15

申请人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Yen-Shih Ho

发明人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC分类号： H01L23/48 ,  H01L21/78 ,  H01L23/31

CPC分类号： H01L23/3128 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

摘要： An embodiment of the invention provides a chip package which includes: a substrate having a plurality of sides and a plurality of corner regions, wherein each of the corner regions is located at an intersection of at least two of the sides of the substrate; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a carrier substrate, wherein the substrate is disposed on the carrier substrate, and the substrate has a recess extending towards the carrier substrate in at least one of the corner regions.

摘要翻译： 本发明的实施例提供一种芯片封装，其包括：具有多个侧面和多个拐角区域的基板，其中每个所述拐角区域位于所述基板的至少两个侧面的相交处; 形成在所述基板中的器件区域; 导电层，其设置在所述基板上并电连接到所述器件区域; 设置在所述基板和所述导电层之间的绝缘层; 以及载体基板，其中所述基板设置在所述载体基板上，并且所述基板具有在至少一个所述拐角区域中朝向所述载体基板延伸的凹部。

公开(公告)号：US08536671B2

公开(公告)日：2013-09-17

申请号：US13154337

申请日：2011-06-06

申请人： Tsang-Yu Liu ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

发明人： Tsang-Yu Liu ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

IPC分类号： H01L31/0203

CPC分类号： H01L27/14623 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L33/44 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/01021 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00

摘要： According to an embodiment of the invention, a chip package is provided, which includes: a substrate having a first surface and a second surface; an optical device between the first surface and the second surface of the substrate; a protection layer formed on the second surface of the substrate, wherein the protection layer has at least an opening; at least a conducting bump formed in the opening of the protection layer and electrically connected to the optical device; and a light shielding layer formed on the protection layer, wherein the light shielding layer is further extended onto a sidewall of the opening of the protection layer.

摘要翻译： 根据本发明的实施例，提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 在所述基板的所述第一表面和所述第二表面之间的光学装置; 形成在所述基板的第二表面上的保护层，其中所述保护层具有至少一个开口; 至少形成在所述保护层的开口中并电连接到所述光学装置的导电凸起; 以及形成在所述保护层上的遮光层，其中所述遮光层进一步延伸到所述保护层的开口的侧壁上。

公开(公告)号：US09136241B2

公开(公告)日：2015-09-15

申请号：US13446954

申请日：2012-04-13

申请人： Yu-Lin Yen ,  Kuo-Hua Liu ,  Yu-Lung Huang ,  Tsang-Yu Liu ,  Yen-Shih Ho

发明人： Yu-Lin Yen ,  Kuo-Hua Liu ,  Yu-Lung Huang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC分类号： H01L23/04 ,  H01L21/50 ,  H01L23/00 ,  H01L23/10

CPC分类号： H01L24/29 ,  H01L23/10 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/29011 ,  H01L2224/29035 ,  H01L2224/29076 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83871 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： An embodiment of the invention provides a manufacturing method of a chip package including: providing a semiconductor wafer having a plurality of device regions separated by a plurality of scribe lines; bonding a package substrate to the semiconductor wafer wherein a spacer layer is disposed therebetween and defines a plurality of cavities respectively exposing the device regions and the spacer layer has a plurality of through holes neighboring the edge of the semiconductor wafer; filling an adhesive material in the through holes wherein the material of the spacer layer is adhesive and different from the adhesive material; and dicing the semiconductor wafer, the package substrate and the spacer layer along the scribe lines to form a plurality of chip packages separated from each other.

摘要翻译： 本发明的实施例提供一种芯片封装的制造方法，包括：提供具有由多个划线分开的多个器件区域的半导体晶片; 将封装衬底接合到半导体晶片，其中间隔层设置在其间并限定分别暴露器件区域并且间隔层具有多个与半导体晶片的边缘相邻的通孔的空腔; 在通孔中填充粘合剂材料，其中间隔层的材料是粘合剂并且不同于粘合剂材料; 并且沿着划线切割半导体晶片，封装衬底和间隔层，以形成彼此分离的多个芯片封装。

公开(公告)号：US08575634B2

公开(公告)日：2013-11-05

申请号：US12981600

申请日：2010-12-30

申请人： Tsang-Yu Liu ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

发明人： Tsang-Yu Liu ,  Yu-Lin Yen ,  Chuan-Jin Shiu ,  Po-Shen Lin

IPC分类号： H01L33/60 ,  H01L33/48

CPC分类号： H01L27/14618 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/16 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a chip package, including: a chip having a semiconductor device thereon; a cap layer over the semiconductor device; a spacer layer between the chip and the cap layer, wherein the spacer layer surrounds the semiconductor device and forms a cavity between the chip and the cap layer; and an anti-reflective layer between the cap layer and the chip, wherein the anti-reflective layer has a overlapping region with the spacer layer and extends into the cavity. Furthermore, a method for fabricating a chip package is also provided.

摘要翻译： 本发明提供了一种芯片封装，包括：其上具有半导体器件的芯片; 半导体器件上的覆盖层; 在所述芯片和所述盖层之间的间隔层，其中所述间隔层围绕所述半导体器件并且在所述芯片和所述盖层之间形成空腔; 以及在所述盖层和所述芯片之间的抗反射层，其中所述抗反射层具有与所述间隔层的重叠区域并延伸到所述空腔中。 此外，还提供了一种用于制造芯片封装的方法。