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104 条记录 (耗时 0.026 秒)

    Method of forming inter-metal interconnection
    1.
    发明授权
    Method of forming inter-metal interconnection 有权
    形成金属间互连的方法

    公开(公告)号：US06352918B1

    公开(公告)日：2002-03-05

    申请号：US09199877

    申请日：1998-11-24

    申请人： Yimin Huang ,  Chih-Chien Liu ,  Tri-Rung Yew

    发明人： Yimin Huang ,  Chih-Chien Liu ,  Tri-Rung Yew

    IPC分类号： H01L21311

    CPC分类号： H01L21/76802

    摘要： A method of forming an inter-metal interconnection is provided. A substrate is provided. A dielectric layer with a metal plug therein is formed on the substrate. An IMD layer is formed on the dielectric layer. An insulating layer and a PE-oxide layer are formed on the IMD layer. A photolithography and etching process is performed to form a trench in the IMD layer and to expose the metal plug in the dielectric layer. A metal is filled into the trench to electrically connect to the metal plug.

    摘要翻译： 提供了形成金属间互连的方法。 提供基板。 在基板上形成有金属塞的电介质层。 在电介质层上形成IMD层。 在IMD层上形成绝缘层和PE-氧化物层。 进行光刻和蚀刻工艺以在IMD层中形成沟槽并露出介电层中的金属插塞。 将金属填充到沟槽中以电连接到金属插头。

    Method of fabricating shallow trench isolation structure
    2.
    发明授权
    Method of fabricating shallow trench isolation structure 有权
    制造浅沟槽隔离结构的方法

    公开(公告)号：US06248644B1

    公开(公告)日：2001-06-19

    申请号：US09301210

    申请日：1999-04-28

    申请人： Gwo-Shii Yang ,  Hsueh-Hao Shih ,  Chih-Chien Liu ,  Tri-Rung Yew

    发明人： Gwo-Shii Yang ,  Hsueh-Hao Shih ,  Chih-Chien Liu ,  Tri-Rung Yew

    IPC分类号： H01L2176

    CPC分类号： H01L21/76235

    摘要： A method of fabricating a shallow trench isolation structure is described. A preserve layer is formed on a substrate. A trench is formed in the substrate and the preserve layer. An oxide layer is formed over the substrate to fill the trench. A wet densification step is performed in a moist environment. A planarization step is performed until the preserve layer is exposed. A shallow trench isolation structure is formed.

    摘要翻译： 描述了制造浅沟槽隔离结构的方法。 在基板上形成保护层。 在衬底和保护层中形成沟槽。 在衬底上形成氧化物层以填充沟槽。 在潮湿的环境中进行湿致密化步骤。 进行平坦化步骤直到保护层被暴露。 形成浅沟槽隔离结构。

    Method for forming shallow trench isolation
    3.
    发明授权
    Method for forming shallow trench isolation 失效
    形成浅沟槽隔离的方法

    公开(公告)号：US06214691B1

    公开(公告)日：2001-04-10

    申请号：US09228932

    申请日：1999-01-12

    申请人： Gwo-Shii Yong ,  Chih-Chien Liu ,  Tri-Rung Yew ,  Water Lur

    发明人： Gwo-Shii Yong ,  Chih-Chien Liu ,  Tri-Rung Yew ,  Water Lur

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224

    摘要： A method for forming shallow trench isolation is disclosed. The method includes forming a trench in a semiconductor substrate, and then blanket depositing a silicon oxide layer over the semiconductor substrate by a plasma process, thereby substantially refilling the trench. Thereafter, a photoresist layer is formed on the plasma deposited silicon oxide layer, followed by etching back a portion of the photoresist layer. The plasma deposited silicon oxide layer is then isotropically etched, and the photoresist layer is then finally removed.

    摘要翻译： 公开了一种用于形成浅沟槽隔离的方法。 该方法包括在半导体衬底中形成沟槽，然后通过等离子体工艺在半导体衬底上覆盖氧化硅层，从而基本上重新填充沟槽。 此后，在等离子体沉积的氧化硅层上形成光致抗蚀剂层，然后蚀刻光致抗蚀剂层的一部分。 然后等离子体沉积的氧化硅层被各向同性地蚀刻，然后最终去除光致抗蚀剂层。

    Process of making unlanded vias
    4.
    发明授权
    Process of making unlanded vias 失效
    制作无人化过孔的过程

    公开(公告)号：US5976984A

    公开(公告)日：1999-11-02

    申请号：US1416

    申请日：1997-12-30

    申请人： Coming Chen ,  Chih-Chien Liu ,  Kun-Chih Wang ,  Tri-Rung Yew

    发明人： Coming Chen ,  Chih-Chien Liu ,  Kun-Chih Wang ,  Tri-Rung Yew

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/02

    CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76829 ,  H01L2924/0002

    摘要： A method of making vias in a semiconductor IC device having adequate contact to the surface of the interconnects and without inadequate landing is disclosed. The method has interconnects formed in a metal layer on the substrate of the IC device, and a first dielectric layer is formed covering the surface of the interconnects. An etch-stopping layer is then formed on top of the first dielectric layer, followed by the formation of a second dielectric layer on top of the etch-stopping layer. A photoresist layer then covers the second dielectric layer and reveals the surface regions of the second dielectric layer designated for the formation of the vias. A main etching procedure is then performed to etch into the second dielectric layer down to the surface of the etch-stopping layer, thereby forming the first section of the vias. An over-etching procedure is then implemented to strip off the etch-stopping layer and further etches into the first dielectric layer and the etching is then stopped when the surface of the interconnects are revealed to conclude the formation of the vias.

    摘要翻译： 公开了一种在半导体IC器件中形成通孔的方法，该半导体IC器件具有与互连表面的充分接触并且没有不足够的着陆。 该方法具有形成在IC器件的衬底上的金属层中的互连，并且覆盖互连表面的第一介电层被形成。 然后在第一介电层的顶部上形成蚀刻停止层，随后在蚀刻停止层的顶部形成第二电介质层。 光致抗蚀剂层然后覆盖第二电介质层并且显露指定用于形成通孔的第二电介质层的表面区域。 然后执行主蚀刻程序以蚀刻到第二介电层中，直到蚀刻停止层的表面，从而形成通孔的第一部分。 然后实施过蚀刻程序以剥离蚀刻停止层并进一步蚀刻到第一介电层中，然后当显露互连表面以终止形成通孔时，停止蚀刻。

    Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit
    5.
    发明授权
    Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit 有权
    用于集成电路中多级互连的布线结构的双镶嵌结构

    公开(公告)号：US07378740B2

    公开(公告)日：2008-05-27

    申请号：US11196038

    申请日：2005-08-02

    申请人： Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

    发明人： Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L21/7681 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.

    摘要翻译： 提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。 在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的二电层和蚀刻停止层。 利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。 利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。

    Method of forming dual damascene structure
    6.
    发明授权
    Method of forming dual damascene structure 有权
    形成双镶嵌结构的方法

    公开(公告)号：US06680248B2

    公开(公告)日：2004-01-20

    申请号：US09991131

    申请日：2001-11-20

    申请人： Yimin Huang ,  Tri-Rung Yew

    发明人： Yimin Huang ,  Tri-Rung Yew

    IPC分类号： H01L214763

    CPC分类号： H01L21/76829 ,  H01L21/76807

    摘要： A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.

    摘要翻译： 形成双镶嵌结构的方法包括以下步骤：提供其上形成有第一导电层的衬底，然后在衬底上顺序形成第一电介质层，抗反射层和第二电介质层。 接下来，对第一电介质层，抗反射层和第二电介质层进行图案化以形成暴露导电层的第一开口。 此后，第二介电层被图案化以在第一导电层上方的位置形成沟槽（或第二开口）。 沟槽和第一开口一起形成双镶嵌结构的开口。 最后，将第二导电材料沉积到开口和沟槽中以形成导电线和双镶嵌结构。

    Method to fabricate a dual metal-damascene structure in a substrate
    8.
    发明授权
    Method to fabricate a dual metal-damascene structure in a substrate 失效
    在基材中制造双金属镶嵌结构的方法

    公开(公告)号：US06027994A

    公开(公告)日：2000-02-22

    申请号：US102083

    申请日：1998-06-22

    申请人： Yimin Huang ,  Tri-Rung Yew

    发明人： Yimin Huang ,  Tri-Rung Yew

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/4763

    CPC分类号： H01L21/76808 ,  H01L23/5226 ,  H01L2221/1031 ,  H01L2924/0002

    摘要： A method to fabricate a dual damascene structure in a substrate is disclosed in the present invention. A first silicon oxide layer is deposited over the substrate and a silicon nitride layer is formed on the first silicon oxide layer. The first silicon oxide layer and the silicon nitride layer are etched in order to form a via hole on the substrate. Afterwards, a second silicon oxide layer is deposited to refill into the via hole and to cover the silicon nitride layer. A dry etching process is performed to remove the second silicon oxide layer in the via hole and to form a metal trench in the second silicon oxide layer on the silicon nitride layer and a metal trench in the second silicon oxide layer above the via hole. After the formation of the metal trenches, a portion of the second silicon oxide layer is remained on the sidewalls and the bottom of the via hole. A dry etching process is performed to remove the remaining portion of the second silicon oxide layer. At last, metal material is deposited to refill into the via hole and the metal trench, it is followed by the metal CMP processs to remove the excess metal over the silicon oxide. The dual metal-damascene structure on the substrate is complete.

    摘要翻译： 在本发明中公开了一种在衬底中制造双镶嵌结构的方法。 在衬底上沉积第一氧化硅层，在第一氧化硅层上形成氮化硅层。 蚀刻第一氧化硅层和氮化硅层以在基板上形成通孔。 然后，沉积第二氧化硅层以重新填充到通孔中并覆盖氮化硅层。 进行干蚀刻处理以去除通孔中的第二氧化硅层，并且在氮化硅层上的第二氧化硅层中形成金属沟槽，在通孔上方的第二氧化硅层中形成金属沟槽。 在形成金属沟槽之后，第二氧化硅层的一部分残留在通孔的侧壁和底部。 执行干蚀刻处理以去除第二氧化硅层的剩余部分。 最后，沉积金属材料以再填充到通孔和金属沟槽中，之后是金属CMP工艺以除去氧化硅上的多余金属。 基板上的双金属镶嵌结构完整。

    Method of manufacturing copper interconnect
    9.
    发明授权
    Method of manufacturing copper interconnect 有权
    制造铜互连的方法

    公开(公告)号：US06265313B1

    公开(公告)日：2001-07-24

    申请号：US09191632

    申请日：1998-11-13

    申请人： Yimin Huang ,  Tri-Rung Yew ,  Water Lur

    发明人： Yimin Huang ,  Tri-Rung Yew ,  Water Lur

    IPC分类号： H01L2144

    CPC分类号： H01L21/76865 ,  H01L21/7681 ,  H01L21/76814 ,  H01L21/76838 ,  H01L21/76844 ,  H01L21/76862 ,  Y10S438/906

    摘要： A method of manufacturing copper interconnects includes the steps of first providing a semiconductor substrate having a dielectric layer thereon. The dielectric layer further includes a copper layer embedded within. An inter-metal dielectric layer is deposited over the dielectric layer. A via opening and a trench opening that exposes a portion of the copper layer are formed in the inter-metal dielectric layer. A thin barrier layer is formed over the exposed copper layer at the bottom of the via opening. The bottom part of the via opening is bombarded by atoms until the copper layer is exposed. Copper material is deposited to fill the via opening and the trench opening, thereby forming a damascene structure.

    摘要翻译： 制造铜互连的方法包括以下步骤：首先在其上提供具有介电层的半导体衬底。 电介质层还包括嵌入其中的铜层。 在介电层上沉积金属间介电层。 在金属间介电层中形成通孔开口和暴露一部分铜层的沟槽开口。 在通孔开口的底部的暴露的铜层上形成薄的阻挡层。 通孔开口的底部被原子轰击直到铜层暴露。 沉积铜材料以填充通孔开口和沟槽开口，从而形成镶嵌结构。

    Method of forming dual damascene structure
    10.
    发明授权
    Method of forming dual damascene structure 失效

    公开(公告)号：US6060379A

    公开(公告)日：2000-05-09

    申请号：US123342

    申请日：1998-07-28

    申请人： Yimin Huang ,  Tri-Rung Yew

    发明人： Yimin Huang ,  Tri-Rung Yew

    IPC分类号： H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/76829 ,  H01L21/76807

    摘要： A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.