公开(公告)号：US08446777B2

公开(公告)日：2013-05-21

申请号：US13280618

申请日：2011-10-25

Applicant: Koki Ueno ,  Eietsu Takahashi ,  Shigefumi Irieda ,  Yasuhiro Shiino ,  Manabu Sakaniwa

Inventor： Koki Ueno ,  Eietsu Takahashi ,  Shigefumi Irieda ,  Yasuhiro Shiino ,  Manabu Sakaniwa

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/14 ,  G11C11/5635 ,  G11C16/16 ,  G11C16/344

Abstract: A non-volatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array and a control unit. The control unit is configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation. The control unit is configured to perform a soft-programming operation of setting the memory cells from an over-erased state to a first threshold voltage distribution state when, in a series of erase operations, the number of erase voltage applications is more than a first number and less than a second number (the first number

Abstract translation: 根据本发明的一个实施例的非易失性半导体存储器件包括存储单元阵列和控制单元。 控制单元被配置为控制擦除操作，擦除验证操作和升压操作的重复。 控制单元被配置为执行将存储单元从过擦除状态设置为第一阈值电压分布状态的软编程操作，当在一系列擦除操作中擦除电压应用的数量多于第一阈值电压分配状态时， 数字和小于第二个数字（第一个数字<第二个数字）。 当擦除电压应用的数量等于或小于第一数量或等于或大于第二数量时，控制单元被配置为不执行软编程操作。

公开(公告)号：US20130058171A1

公开(公告)日：2013-03-07

申请号：US13425121

申请日：2012-03-20

Applicant: Yasuhiro SHIINO ,  Shigefumi Irieda ,  Kenri Nakai ,  Eietsu Takahashi ,  Koki Ueno

Inventor： Yasuhiro SHIINO ,  Shigefumi Irieda ,  Kenri Nakai ,  Eietsu Takahashi ,  Koki Ueno

IPC: G11C16/06 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3418

Abstract: A semiconductor storage device has a plurality of memory cells each having a control gate that are formed on a well. The semiconductor storage device has a control circuit that applies a voltage to the well and the control gates.In an erase operation of the memory cell, the control circuit applies a first pulse wave of a first erasure voltage that rises stepwise to the well and then applies a second pulse wave of a second erasure voltage to the well.

Abstract translation: 半导体存储装置具有多个存储单元，每个存储单元具有形成在阱上的控制栅极。 半导体存储装置具有向井和控制门施加电压的控制电路。 在存储单元的擦除操作中，控制电路施加第一擦除电压的第一脉冲波，该第一脉冲波逐步上升到阱，然后向阱施加第二擦除电压的第二脉冲波。

公开(公告)号：US20120281477A1

公开(公告)日：2012-11-08

申请号：US13308736

申请日：2011-12-01

Applicant: Manabu Sakaniwa ,  Koki Ueno ,  Shigefumi Irieda ,  Eietsu Takahashi ,  Yasuhiro Shiino ,  Daisuke Kouno

Inventor： Manabu Sakaniwa ,  Koki Ueno ,  Shigefumi Irieda ,  Eietsu Takahashi ,  Yasuhiro Shiino ,  Daisuke Kouno

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/3427

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array includes a plurality of cell units each composed of a plurality of memory cells which are arranged at intersections of a plurality of bit lines and a plurality of word lines and whose current paths are connected in series and select transistors each connected to either end of the series connection, a voltage generator circuit which generates a voltage applied to the memory cell array, and a control circuit which controls the memory cell array and the voltage generator circuit.

Abstract translation: 根据一个实施例，半导体存储器件包括存储单元阵列，其包括多个单元单元，每个单元单元由多个存储单元构成，多个存储单元布置在多个位线和多个字线的交点处，并且其电流路径为 串联连接的晶体管和串联连接的任一端的晶体管，产生施加到存储单元阵列的电压的电压发生器电路以及控制存储单元阵列和电压发生器电路的控制电路。

公开(公告)号：US08953371B2

公开(公告)日：2015-02-10

申请号：US13425121

申请日：2012-03-20

Applicant: Yasuhiro Shiino ,  Shigefumi Irieda ,  Kenri Nakai ,  Eietsu Takahashi ,  Koki Ueno

Inventor： Yasuhiro Shiino ,  Shigefumi Irieda ,  Kenri Nakai ,  Eietsu Takahashi ,  Koki Ueno

IPC: G11C11/34 ,  G11C11/56 ,  G11C16/06 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3418

Abstract: A semiconductor storage device has a plurality of memory cells each having a control gate that are formed on a well. The semiconductor storage device has a control circuit that applies a voltage to the well and the control gates.In an erase operation of the memory cell, the control circuit applies a first pulse wave of a first erasure voltage that rises stepwise to the well and then applies a second pulse wave of a second erasure voltage to the well.

Abstract translation: 半导体存储装置具有多个存储单元，每个存储单元具有形成在阱上的控制栅极。 半导体存储装置具有向井和控制门施加电压的控制电路。 在存储单元的擦除操作中，控制电路施加第一擦除电压的第一脉冲波，该第一脉冲波逐步上升到阱，然后向阱施加第二擦除电压的第二脉冲波。

公开(公告)号：US08385126B2

公开(公告)日：2013-02-26

申请号：US13246004

申请日：2011-09-27

Applicant: Yasuhiro Shiino ,  Eietsu Takahashi ,  Koki Ueno

Inventor： Yasuhiro Shiino ,  Eietsu Takahashi ,  Koki Ueno

IPC: G11C16/04

CPC classification number: G11C16/26 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/3427 ,  G11C16/349

Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.

公开(公告)号：US08976597B2

公开(公告)日：2015-03-10

申请号：US13227050

申请日：2011-09-07

Applicant: Yasuhiro Shiino ,  Eietsu Takahashi ,  Koki Ueno

Inventor： Yasuhiro Shiino ,  Eietsu Takahashi ,  Koki Ueno

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/16 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/3445 ,  G11C16/345

Abstract: A control circuit executes an erase operation that includes an erase pulse application operation and an erase verify operation. The erase pulse application operation applies an erase pulse voltage to a memory cell to change the memory cell from a write state to an erase state. The erase verify operation applies an erase verify voltage to the memory cell to judge whether the memory cell is in the erase state or not. The control circuit changes conditions of execution of the erase verify operation when the number of times of executions of the erase pulse application operation in one erase operation reaches a first number.

Abstract translation: 控制电路执行包括擦除脉冲施加操作和擦除验证操作的擦除操作。 擦除脉冲施加操作将擦除脉冲电压施加到存储单元，以将存储单元从写入状态改变为擦除状态。 擦除验证操作将擦除验证电压施加到存储器单元以判断存储器单元是否处于擦除状态。 当在一个擦除操作中执行擦除脉冲施加操作的次数达到第一数量时，控制电路改变擦除验证操作的执行条件。

公开(公告)号：US20120281487A1

公开(公告)日：2012-11-08

申请号：US13288485

申请日：2011-11-03

Applicant: Manabu SAKANIWA ,  Koki Ueno ,  Shigefumi Irieda ,  Eietsu Takahashi ,  Yasuhiro Shiino

Inventor： Manabu SAKANIWA ,  Koki Ueno ,  Shigefumi Irieda ,  Eietsu Takahashi ,  Yasuhiro Shiino

IPC: G11C7/22

CPC classification number: G11C16/10 ,  G11C16/0483

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array includes a plurality of memory cell units which are arranged at intersections of a plurality of bit lines and a plurality of word lines and whose current paths are connected in series, a voltage generator circuit which generates a voltage to be applied to the memory cell array, and a control circuit which controls the memory cell array and the voltage generator circuit. The control circuit, when writing data into the memory cell array, performs control so as to apply a first write pass voltage to unselected word lines in the memory cell units and, after a selected word line has reached a write voltage, further apply a voltage to the unselected word lines until a second write pass voltage higher than the first write pass voltage has been reached.

Abstract translation: 根据一个实施例，一种半导体存储器件包括：存储单元阵列，包括布置在多个位线和多个字线的交点处并且其电流通路串联连接的多个存储单元单元;电压发生器 产生施加到存储单元阵列的电压的电路，以及控制存储单元阵列和电压发生器电路的控制电路。 控制电路在将数据写入存储单元阵列时进行控制，以对存储单元单元中的未选字线施加第一写入通过电压，并且在所选字线达到写入电压之后，进一步施加电压 到未选择的字线，直到达到高于第一写入通过电压的第二写入通过电压。

公开(公告)号：US10166953B2

公开(公告)日：2019-01-01

申请号：US13510967

申请日：2010-11-05

Applicant: Takahiko Tsutsumi ,  Keisuke Sekiya ,  Koki Ueno ,  Ichiro Kitaori ,  Toshinari Suzuki

Inventor： Takahiko Tsutsumi ,  Keisuke Sekiya ,  Koki Ueno ,  Ichiro Kitaori ,  Toshinari Suzuki

IPC: B60T1/00 ,  B60L11/14 ,  F16H63/48 ,  B60L11/18 ,  F16H63/42 ,  F16H59/74

Abstract: When a P lock state is set on the basis of a predetermined request signal for setting the P lock state, a P position indicator lamp (62) is turned on or off on the basis of the status of power supplied to the vehicle (10). For example, when the P lock state is set, the P position indicator lamp (62) is turned off when the power status is an ALL-OFF status where a combination meter (56), or the like, is not turned on or is raised to an ACC-ON status; whereas, when the P lock state is set, the P position indicator lamp (62) is turned on when the power status is an IG-ON status, when the power status is changed from the IG-ON status during vehicle driving to the ACC-ON status, or within a predetermined period of time from when the power status is changed from the IG-ON status to the ALL-OFF status.

公开(公告)号：US08814752B2

公开(公告)日：2014-08-26

申请号：US13529259

申请日：2012-06-21

Applicant: Ichiro Kitaori ,  Takahiko Tsutsumi ,  Osamu Kanai ,  Koki Ueno ,  Keisuke Sekiya ,  Toshinari Suzuki

Inventor： Ichiro Kitaori ,  Takahiko Tsutsumi ,  Osamu Kanai ,  Koki Ueno ,  Keisuke Sekiya ,  Toshinari Suzuki

IPC: F16H59/74

CPC classification number: F16H63/3466 ,  F16H59/10 ,  F16H63/483

Abstract: It is provided a shift control device for a vehicle having a parking lock device driven by an actuator to selectively switch switching positions between a lock position and an unlock position, wherein when a run-enable operation is made by a driver and a non-running state is switched to a running state, shift position recognizing control is executed for recognizing an initial switching position appearing at the beginning when the running state is established, by driving the actuator in response to switching position information indicative of the switching position on a stage before the running state is established, wherein: the non-running state is configured to be switched to the running state prior to the execution of the run-enable operation; and updating of the switching position information, stored in the switching position information storage device, is permitted to be executed subjected to the switching position recognizing control being executed.

Abstract translation: 提供一种用于车辆的变速控制装置，具有由致动器驱动的驻车锁定装置，以选择性地切换锁定位置和解锁位置之间的切换位置，其中当驾驶员进行行驶使能操作和不运行时 状态切换到运行状态，通过根据在前面的台上指示切换位置的切换位置信息来驱动致动器，执行换档位置识别控制，以识别在运行状态建立时开始时出现的初始切换位置 建立运行状态，其中：非运行状态被配置为在执行运行使能操作之前切换到运行状态; 并且存储在切换位置信息存储装置中的切换位置信息的更新被允许执行经过执行的切换位置识别控制。

公开(公告)号：US08174899B2

公开(公告)日：2012-05-08

申请号：US13087744

申请日：2011-04-15

Applicant: Koki Ueno

Inventor： Koki Ueno

IPC: G11C16/00

CPC classification number: G11C16/3436 ,  G11C16/32

Abstract: When data is written to a memory cell transistor, a write controller controls in such a manner that a verification operation subsequent to a program operation is carried out while a program voltage is increased stepwise for each program operation. The write controller controls in such a manner that a verification operation subsequent to a program operation by which a threshold voltage of a memory cell transistor to be written has become equal to or higher than a verification level for the first time is carried out twice or more at the same verification level, verification operations of the second and subsequent times are carried out after a second program operation which is carried out with the memory cell transistor set in an unselected state.

Abstract translation: 当数据被写入存储单元晶体管时，写入控制器以这样一种方式进行控制，使得在对每个编程操作逐步增加编程电压的同时执行编程操作之后的验证操作。 写入控制器以这样的方式进行控制，使得要写入的存储单元晶体管的阈值电压的编程操作之后的验证操作已经变为等于或高于第一次的验证电平两次或更多次 在相同的验证级别，在存储单元晶体管设置为未选择状态的第二编程操作之后执行第二次和随后时间的验证操作。