公开(公告)号：US20070114634A1

公开(公告)日：2007-05-24

申请号：US11553949

申请日：2006-10-27

申请人： Yaojian Lin ,  Haijing Cao ,  Robert Frye ,  Pandi Marimuthu

发明人： Yaojian Lin ,  Haijing Cao ,  Robert Frye ,  Pandi Marimuthu

IPC分类号： H01L29/00

CPC分类号： H01L23/66 ,  H01L23/50 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05027 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/13 ,  H01L2924/1305 ,  H01L2924/19011 ,  H01L2924/00 ,  H01L2924/00014

摘要： An integrated passive device system is disclosed including forming a first dielectric layer over a semiconductor substrate, depositing a metal capacitor layer and a silicide layer on the first dielectric layer, forming a second dielectric layer over the metal capacitor layer and the silicide layer, and depositing a metal layer over the second dielectric layer for forming the integrated capacitor, an integrated resistor, an integrated inductor, or a combination thereof.

摘要翻译： 公开了一种集成的无源器件系统，包括在半导体衬底上形成第一电介质层，在第一电介质层上沉积金属电容器层和硅化物层，在金属电容器层和硅化物层上形成第二电介质层， 用于形成集成电容器的第二电介质层上的金属层，集成电阻器，集成电感器或其组合。

公开(公告)号：US20070114651A1

公开(公告)日：2007-05-24

申请号：US11538806

申请日：2006-10-04

申请人： Pandi Marimuthu ,  Robert Frye ,  Yaojian Lin

发明人： Pandi Marimuthu ,  Robert Frye ,  Yaojian Lin

IPC分类号： H01L23/48 ,  H01L23/34

CPC分类号： H01L23/645 ,  H01F2017/0046 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19051 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

摘要： An integrated circuit stacking system is provided including fabricating an integrated passive device including: providing a semiconductor substrate, forming an integrated inductor, a resistor block, or an integrated capacitor integrated on the semiconductor substrate, and forming contact pads, on the semiconductor substrate, coupled to the integrated inductor, the resistor block, or the integrated capacitor; positioning an integrated circuit die for maintaining an inductor spacing; mounting the integrated circuit die on the integrated passive device; and encapsulating the integrated circuit die and the integrated passive device.

摘要翻译： 提供一种集成电路堆叠系统，包括制造集成无源器件，包括：提供半导体衬底，形成集成电感器，电阻器块或集成在半导体衬底上的集成电容器，以及在半导体衬底上形成接触焊盘， 集成电感，电阻块或集成电容; 定位用于保持电感器间距的集成电路管芯; 将集成电路管芯安装在集成无源器件上; 并封装集成电路管芯和集成无源器件。

公开(公告)号：US20070284726A1

公开(公告)日：2007-12-13

申请号：US11843649

申请日：2007-08-23

申请人： Yaojian Lin ,  Pandi Marimuthu

发明人： Yaojian Lin ,  Pandi Marimuthu

IPC分类号： H01L23/50 ,  H01L21/60

CPC分类号： H01L23/525 ,  H01L23/5227 ,  H01L23/53223 ,  H01L23/53238 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

摘要： An integrated circuit package system including: providing an integrated circuit die, forming a first layer over the integrated circuit die, forming a bridge on and in the first layer, forming a second layer on the first layer, and forming bump pads on and in the second layer, the bump pads connected to ends of the bridge.

摘要翻译： 一种集成电路封装系统，包括：提供集成电路管芯，在所述集成电路管芯上形成第一层，在所述第一层上并在所述第一层中形成桥，在所述第一层上形成第二层， 第二层，凸块连接到桥的端部。

公开(公告)号：US20070235878A1

公开(公告)日：2007-10-11

申请号：US11278002

申请日：2006-03-30

申请人： Yaojian Lin ,  Pandi Marimuthu

发明人： Yaojian Lin ,  Pandi Marimuthu

IPC分类号： H01L23/48

CPC分类号： H01L23/525 ,  H01L23/5227 ,  H01L23/53223 ,  H01L23/53238 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/13022 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2924/14 ,  H01L2924/00

摘要： An integrated circuit package system is provided providing an integrated circuit die having a final metal layer of the semiconductor process used to manufacture the integrated circuit die and a passivation layer provided thereon, depositing a first metal layer on the passivation layer and the final metal layer, forming an analog circuit in the first metal layer, coating a first insulation layer on the first metal layer and the passivation layer, exposing a first pad and a second pad of the first metal layer through the first insulation layer, and connecting a first interconnect on the first pad and a second interconnect on the second pad.

摘要翻译： 提供一种集成电路封装系统，提供具有用于制造集成电路管芯的半导体工艺的最终金属层和设置在其上的钝化层的集成电路管芯，在钝化层和最终金属层上沉积第一金属层， 在所述第一金属层中形成模拟电路，在所述第一金属层和所述钝化层上涂覆第一绝缘层，通过所述第一绝缘层暴露所述第一金属层的第一焊盘和第二焊盘，以及将第一互连 第一焊盘和第二焊盘上的第二互连。

公开(公告)号：US20070080437A1

公开(公告)日：2007-04-12

申请号：US11234528

申请日：2005-09-22

申请人： Pandi Marimuthu ,  Il Shim

发明人： Pandi Marimuthu ,  Il Shim

IPC分类号： H01L23/495

CPC分类号： H01L25/105 ,  H01L21/561 ,  H01L23/4334 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit package system is provided including forming a leadframe structure having a encapsulant space provided predominantly inside the leadframe structure and attaching a die to the leadframe structure in the encapsulant space inside the leadframe structure. The system further includes electrically connecting the die to the leadframe structure and injecting encapsulant into the encapsulant space to form the integrated circuit package system.

摘要翻译： 提供了一种集成电路封装系统，包括形成引线框架结构，该引线框架结构具有主要位于引线框架结构内部的封装空间，并将管芯附接到引线框架结构内密封空间中的引线框架结构。 该系统还包括将管芯与引线框结构电连接并将密封剂注入密封空间以形成集成电路封装系统。

公开(公告)号：US20060175689A1

公开(公告)日：2006-08-10

申请号：US11053564

申请日：2005-02-08

申请人： Il Kwon Shim ,  Seng Guan Chow ,  Jeffrey Punzalan ,  Pandi Marimuthu

发明人： Il Kwon Shim ,  Seng Guan Chow ,  Jeffrey Punzalan ,  Pandi Marimuthu

IPC分类号： H01L23/495 ,  H01L21/50

CPC分类号： H01L23/49568 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A multi-leadframe semiconductor package and method of manufacture includes a first leadframe having a die pad and a plurality of contact leads around the periphery of the die pad. A die is attached to the die pad and electrically connected to the plurality of contact leads. A heat spreader leadframe having a heat spreader and a plurality of terminal leads around the periphery of the heat spreader is provided. The die pad is attached to the heat spreader, and the plurality of contact leads is attached to the plurality of terminal leads.

公开(公告)号：US20050263861A1

公开(公告)日：2005-12-01

申请号：US11007896

申请日：2004-12-08

申请人： Byung Ahn ,  Pandi Marimuthu

发明人： Byung Ahn ,  Pandi Marimuthu

IPC分类号： H01L23/495

CPC分类号： H01L23/49503 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/27013 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An integrated circuit leadframe and a fabrication method for fabricating the integrated circuit leadframe include forming a leadframe having leads around a die pad that has a peripheral die pad rim. A discrete, alternately staggered surface configuration is formed in the die pad rim. The discrete, alternately staggered surface configuration creates space in the die pad for connecting and separating ground bond wire-bonds and down bond wire-bonds, and provides for locking encapsulant firmly to the die pad.

摘要翻译： 集成电路引线框架和用于制造集成电路引线框架的制造方法包括形成具有围绕具有周边芯片焊盘边缘的管芯焊盘周围的引线的引线框架。 在芯片焊盘边缘中形成离散的，交替错开的表面构型。 离散的，交错交错的表面构造在管芯焊盘中形成空间，用于连接和分离接地引线接合和下接合引线接合，并且将密封剂牢固地锁定到管芯焊盘。