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公开(公告)号：US20190326335A1
公开(公告)日：2019-10-24
申请号：US16097279
申请日：2018-09-18
Inventor： Guanghui Liu , Peng He , Yong Xu , Fei Ai
IPC: H01L27/12
Abstract: A manufacturing method for TFT array substrate and TFT array substrate are disclosed. After depositing an electrode material layer and a metal material layer on the gate insulation layer and the active layer in sequence after the active layer above the gate electrode is formed. A photoresist pattern is formed on the metal material layer. The photoresist pattern includes a first and second photoresist blocks with different thicknesses. The metal material layer and the electrode material layer are etched using the photoresist pattern to form a contact electrode and pixel electrodes connected with two ends of the active layer and the source/drain electrodes on the contact electrode. The process is simple and can effectively reduce the contact resistance between the source/drain and the active layer and improve the quality of the product.
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公开(公告)号：US12094888B2
公开(公告)日：2024-09-17
申请号：US17278722
申请日：2021-02-05
Inventor： Tao Ma , Yong Xu , Wanglin Wen , Fei Ai
IPC: H01L27/12 , H01L29/786
CPC classification number: H01L27/1244 , H01L27/1222 , H01L27/1288 , H01L29/78675
Abstract: An array substrate includes a substrate, a first metal layer and an active layer disposed on the substrate, an interlayer insulating layer, and a second metal layer. The first metal layer forms at least one first trace, the interlayer insulating layer is disposed on the first metal layer and the active layer, the second metal layer is disposed on the interlayer insulating layer, the interlayer insulating layer is formed with a first contact hole, and the second metal layer is connected to the first trace through the first contact hole. The first metal layer includes a conductive layer and a first protective layer stacked in sequence.
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公开(公告)号：US12087080B2
公开(公告)日：2024-09-10
申请号：US17419621
申请日：2021-05-24
Inventor： Wanglin Wen , Fei Ai , Yong Xu
IPC: G06V40/13 , H01L25/16 , H01L27/146
CPC classification number: G06V40/1318 , G06V40/1306 , H01L25/167 , H01L27/14636 , H01L27/14643
Abstract: A display panel and a manufacturing method thereof are provided. A fingerprint recognition module and a storage capacitor of the display panel are disposed in a thin-film transistor (TFT) device layer. The fingerprint recognition module is electrically connected to an active layer and the storage capacitor of a TFT by an electrode layer, thereby optimizing a structure of an array substrate. Furthermore, the display panel can better receive reflected light signals and has improved fingerprint recognition performance. The display panel has a simple manufacturing process and low manufacturing costs.
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公开(公告)号：US12068330B2
公开(公告)日：2024-08-20
申请号：US16966116
申请日：2020-01-17
Inventor： Yuan Yan , Yong Xu , Fei Ai , Dewei Song
CPC classification number: H01L27/124 , G06F3/041 , G06F3/0412 , G06F3/04164 , G06F3/0443 , H01L27/1288 , G06F2203/04103
Abstract: A touch array substrate and a manufacturing method thereof, wherein in the touch array substrate, an active layer, an insulating layer, a pixel electrode layer, a metal layer, a planarization layer, and a common electrode layer are sequentially disposed on the buffer layer. The active layer includes a first region corresponding to a source electrode and a second region corresponding to a drain electrode. The pixel electrode layer includes a plurality of base layers. The metal layer is correspondingly disposed on the base layers. The metal layer includes a touch signal line, a data line, and a gate electrode. The common electrode layer includes a touch electrode, the source electrode, and the drain electrode.
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公开(公告)号：US11796847B2
公开(公告)日：2023-10-24
申请号：US17600321
申请日：2021-08-19
IPC: G02F1/1333 , G02F1/1362 , G02F1/1343 , H01L27/12 , H01L29/786 , H01L29/66
CPC classification number: G02F1/133345 , G02F1/133357 , G02F1/134309 , G02F1/136204 , H01L27/1222 , H01L27/1274 , H01L29/66757 , H01L29/78675 , G02F2201/07
Abstract: An array substrate, includes: a substrate, a first metal layer, a first buffer layer, and an active layer, a gate insulating layer, a second metal layer, a first insulating layer, a third metal layer and a first planarization layer. The first metal layer is electrically connected with the first doped area of the active layer through the bridge layer of the second metal layer. The third metal layer is electrically connected with the second doped area of the active layer. The array substrate of the present disclosure reduces a size of a thin film transistor by stacking the first metal layer, the second metal layer, and the third metal layer, thereby increasing pixel density. A display panel is also provided.
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Patent Agency Ranking
公开(公告)号：US10971530B2
公开(公告)日：2021-04-06
申请号：US16097279
申请日：2018-09-18
Inventor： Guanghui Liu , Peng He , Yong Xu , Fei Ai
IPC: H01L27/12
Abstract: A manufacturing method for TFT array substrate and TFT array substrate are disclosed. After depositing an electrode material layer and a metal material layer on the gate insulation layer and the active layer in sequence after the active layer above the gate electrode is formed. A photoresist pattern is formed on the metal material layer. The photoresist pattern includes a first and second photoresist blocks with different thicknesses. The metal material layer and the electrode material layer are etched using the photoresist pattern to form a contact electrode and pixel electrodes connected with two ends of the active layer and the source/drain electrodes on the contact electrode. The process is simple and can effectively reduce the contact resistance between the source/drain and the active layer and improve the quality of the product.
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公开(公告)号：US20170160611A1
公开(公告)日：2017-06-08
申请号：US14888451
申请日：2015-10-26
Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Yong Xu
IPC: G02F1/1362 , H01L29/786 , G02F1/1368
CPC classification number: G02F1/136209 , G02F1/136213 , G02F1/136227 , G02F1/1368 , G02F2001/136231 , G02F2001/13685 , G02F2202/104 , H01L27/124 , H01L27/1255 , H01L29/78621 , H01L29/78633 , H01L29/78675
Abstract: The present invention provides a LTPS TFT substrate, which includes a black matrix arranged on a first buffer layer of the LTPS TFT substrate to have an area where a TFT device is located is shielded by the black matrix thereby preventing the TFT device from being influenced by light irradiation, maintaining stability of the TFT device; and also saving the manufacturing process of a shielding metal layer, reducing one photo-mask, and lowering down manufacturing cost so as to allow the black matrix, in achieving the functionality of its own (shielding leaking light of the pixel), to also take the place of a shielding metal layer that is commonly adopted in the prior art to shield light for the TFT device and thus providing duality of functionality.
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公开(公告)号：US11862642B2
公开(公告)日：2024-01-02
申请号：US16966119
申请日：2020-04-20
Inventor： Juncheng Xiao , Yong Xu , Fei Ai , Dewei Song
CPC classification number: H01L27/1225 , H01L27/1285 , H01L27/1288
Abstract: A display panel, an array substrate, and a manufacturing method thereof, wherein the array substrate includes a thin film transistor device, and an interface layer, a first transparent conductive layer, a passivation layer, and a second transparent conductive layer which are formed on the thin film transistor device in sequence. By replacing a planarization layer in the prior art with the interface layer, performing a gate re-etching process, and perforating the interface layer and the passivation layer to simultaneously form a deep via and a shallow via, a number of photomasks required to form the array substrate is reduced to 8. It effectively reduces costs of production materials and costs of photomasks.
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公开(公告)号：US11307468B2
公开(公告)日：2022-04-19
申请号：US16754332
申请日：2019-11-11
Inventor： Yuan Yan , Yong Xu , Dewei Song , Fei Ai
IPC: G02F1/1362 , H01L27/12 , G02F1/1333 , G06F3/041 , G02F1/1343
Abstract: The present disclosure provides an array substrate and a manufacturing method of the array substrate. The method includes sequentially forming an active layer and an insulating layer on a substrate; forming a common electrode layer and a first metal layer on the insulating layer using a same photomask, wherein the common electrode layer includes touch electrodes; and forming a second metal layer on the pixel electrode layer, wherein the second metal layer includes touch signal lines, and the touch signal lines electrically are electrically connected to the touch electrodes.
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公开(公告)号：US20220004066A1
公开(公告)日：2022-01-06
申请号：US16754332
申请日：2019-11-11
Inventor： Yuan Yan , Yong Xu , Dewei Song , Fei Ai
IPC: G02F1/1362 , H01L27/12 , G02F1/1343 , G02F1/1333 , G06F3/041
Abstract: The present disclosure provides an array substrate and a manufacturing method of the array substrate. The method includes sequentially forming an active layer and an insulating layer on a substrate; forming a common electrode layer and a first metal layer on the insulating layer using a same photomask, wherein the common electrode layer includes touch electrodes; and forming a second metal layer on the pixel electrode layer, wherein the second metal layer includes touch signal lines, and the touch signal lines electrically are electrically connected to the touch electrodes.
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