公开(公告)号：US20060255850A1

公开(公告)日：2006-11-16

申请号：US11491701

申请日：2006-07-24

申请人： Wing Luk ,  Leland Chang ,  Robert Dennard ,  Robert Montoye

发明人： Wing Luk ,  Leland Chang ,  Robert Dennard ,  Robert Montoye

IPC分类号： H03K3/356

CPC分类号： G11C7/065 ,  G11C7/06 ,  H03F1/56 ,  H03F3/10 ,  H03F3/347 ,  H03F2200/183

摘要： A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.

摘要翻译： 读出放大器电路包括（1）隔离装置，其包括控制端子和第一和第二端子，隔离装置的第一端子耦合到信号线，（2）门控二极管，包括第一和第二端子，第一端子 所述门控二极管耦合到隔离装置的第二端子，并且门控二极管的第二端子耦合到设定线路; 和（3）耦合到隔离装置的控制端子并且适于控制隔离装置的控制端子上的电压的控制电路，以便启用和禁用隔离装置。 闩锁电路还包括预充电装置，其包括控制端子和第一和第二端子，预充电装置的第一端子耦合到电源电压，并且预充电装置的第二端子耦合到隔离装置的第一端子。

公开(公告)号：US20060050581A1

公开(公告)日：2006-03-09

申请号：US10933706

申请日：2004-09-03

申请人： Wing Luk ,  Leland Chang ,  Robert Dennard ,  Robert Montoye

发明人： Wing Luk ,  Leland Chang ,  Robert Dennard ,  Robert Montoye

IPC分类号： G11C7/00

CPC分类号： G11C7/065 ,  G11C7/06 ,  H03F1/56 ,  H03F3/10 ,  H03F3/347 ,  H03F2200/183

摘要： A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.

公开(公告)号：US20070164359A1

公开(公告)日：2007-07-19

申请号：US11334170

申请日：2006-01-18

申请人： Leland Chang ,  Robert Dennard ,  David Fried ,  Wing Luk

发明人： Leland Chang ,  Robert Dennard ,  David Fried ,  Wing Luk

IPC分类号： H01L27/12

CPC分类号： H01L29/7391 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823487

摘要： An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, and at least one trench electrode extending substantially vertically through the active region and at least partially into the semiconductor layer. A first terminal of the gated diode is electrically connected to the trench electrode, and at least a second terminal is electrically connected to the active region. The gated diode is operative in one of at least a first mode and a second mode as a function of a voltage potential applied between the first and second terminals. The first mode is characterized by the creation of an inversion layer in the semiconductor layer substantially surrounding the trench electrode. The gated diode has a first capacitance in the first mode and a second capacitance in the second mode, the first capacitance being substantially greater than the second capacitance.

摘要翻译： 区域有效的门控二极管包括第一导电类型的半导体层，形成在靠近半导体层的上表面的半导体层中的第二导电类型的有源区，以及至少一个沟槽电极，该沟槽电极基本垂直延伸穿过活性层 并且至少部分地进入半导体层。 门控二极管的第一端子电连接到沟槽电极，并且至少第二端子电连接到有源区域。 门控二极管作为施加在第一和第二端子之间的电压电位的函数的至少第一模式和第二模式中的一个工作。 第一模式的特征在于在基本上围绕沟槽电极的半导体层中产生反型层。 门控二极管具有第一模式中的第一电容和第二模式中的第二电容，第一电容基本上大于第二电容。

公开(公告)号：US20060039179A1

公开(公告)日：2006-02-23

申请号：US11248863

申请日：2005-10-12

申请人： Wing Luk ,  Robert Dennard ,  Stephen Kosonocky

发明人： Wing Luk ,  Robert Dennard ,  Stephen Kosonocky

IPC分类号： G11C11/24

CPC分类号： G11C5/063 ,  G11C11/406 ,  G11C11/4074 ,  G11C2207/104

摘要： An integrated circuit, such as a memory macro, includes multiple power rails supporting first and second voltage differentials, with the second voltage differential being smaller than the first voltage differential. Signal lines in the integrated circuit are driven with the small voltage swing, which is generated by small swing circuits. The integrated circuit further includes regeneration circuits, which are receiving small voltage swing inputs and are outputting first, or full voltage swings. The application of the small voltage swing to the signal lines saves power in the integrated circuit. A wide bandwidth, full-wordline I/O, memory integrated circuit has simultaneously operable connection paths between essentially all the memory cells that are attached to the same wordline and the corresponding I/O terminals, and it has a single ended data-line structure.

摘要翻译： 诸如存储器宏的集成电路包括支持第一和第二电压差的多个电源轨，第二电压差小于第一电压差。 集成电路中的信号线由小的摆动电路产生的小电压摆动驱动。 集成电路还包括正在接收小电压摆幅输入并且正在输出第一或全电压摆幅的再生电路。 将小电压摆幅应用于信号线节省了集成电路中的功率。 宽带宽全字I / O存储器集成电路具有在连接到相同字线和对应的I / O端子的基本上所有存储单元之间的同时可操作的连接路径，并且具有单端数据线结构 。

公开(公告)号：US20050052897A1

公开(公告)日：2005-03-10

申请号：US10656596

申请日：2003-09-05

申请人： Wing Luk ,  Robert Dennard

发明人： Wing Luk ,  Robert Dennard

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C11/24 ,  G11C11/4091

CPC分类号： G11C7/1039 ,  G11C7/067 ,  G11C11/4091 ,  G11C2207/104

摘要： A DRAM is disclosed which includes a single ended bitline structure, a single ended global bitline structure, primary sense amplifiers with data storage and data write-back capability and with capability to decouple from the global bitlines, a full-wordline I/O structure where essentially all memory cell that belong to the same wordline are being operated on, and a pipelined architecture. The DRAM further includes a small voltage swing design. The primary sense amplifiers can include more than one amplification stages. Such a DRAM is suitable for applications in conjunction with processors as an embedded DRAM.

摘要翻译： 公开了一种DRAM，其包括单端位线结构，单端全局位线结构，具有数据存储和数据回写能力的初级读出放大器，以及具有与全局位线分离的能力的全字I / O结构，其中 基本上所有属于相同字线的所有存储器单元正在被操作，以及流水线架构。 DRAM还包括小电压摆幅设计。 主感测放大器可以包括多于一个的放大级。 这样的DRAM适用于作为嵌入式DRAM的处理器的应用。

公开(公告)号：US20050146928A1

公开(公告)日：2005-07-07

申请号：US10751713

申请日：2004-01-05

申请人： Wing Luk ,  Robert Dennard

发明人： Wing Luk ,  Robert Dennard

IPC分类号： H01L21/82 ,  G11C11/36 ,  G11C11/405 ,  G11C11/407 ,  H01L27/04 ,  H01L27/10 ,  H01L27/102 ,  H01L27/108 ,  H01L29/739

CPC分类号： H01L27/108 ,  G11C11/405 ,  H01L27/1021 ,  H01L29/7391

摘要： A memory cell comprises: (1) a write switch, the first terminal of the write switch coupled to an at least one bitline, the control terminal of the write switch coupled to the first control line; (2) a two terminal semiconductor, the first terminal of the two terminal semiconductor device coupled to the second terminal of the write switch, and the second terminal of the two terminal semiconductor device coupled to an at least one second control line, wherein the two terminal semiconductor device has a capacitance when a voltage on the first terminal relative to the second terminal is above a threshold voltage and has a lower capacitance when the voltage on the first terminal relative to the second terminal is less than the threshold voltage; (3) a read select switch, the control terminal of the read select switch coupled to an at least one second control line, the first terminal of the read select switch coupled to the at least one bitline; and (4) a read switch, the control terminal of the read switch coupled to the first terminal of the gated diode and coupled to the second terminal of the write switch, the first terminal of the read switch coupled to the second terminal of the read select gate, and the second terminal of the read switch coupled to ground.

摘要翻译： 存储器单元包括：（1）写开关，写开关的第一端耦合到至少一个位线，写开关的控制端耦合到第一控制线; （2）二端子半导体，耦合到写开关的第二端的两端子半导体器件的第一端子和耦合到至少一个第二控制线的两端子半导体器件的第二端子，其中两 当所述第一端子上的电压相对于所述第二端子的电压高于阈值电压并且当所述第一端子上的相对于所述第二端子的电压小于所述阈值电压时，所述端子半导体器件具有较小的电容; （3）读选择开关，所述读选择开关的控制端耦合到至少一个第二控制线，所述读选择开关的第一端耦合到所述至少一位线; 和（4）读取开关，读取开关的控制端子耦合到门控二极管的第一端子并耦合到写入开关的第二端子，读取开关的第一端子耦合到读取的第二端子 选择门，读取开关的第二个端子耦合到地。

公开(公告)号：US20050145895A1

公开(公告)日：2005-07-07

申请号：US10751714

申请日：2004-01-05

申请人： Wing Luk ,  Robert Dennard

发明人： Wing Luk ,  Robert Dennard

IPC分类号： G11C7/06 ,  H01L27/08 ,  H01L29/739 ,  H03F1/56 ,  H01L21/336 ,  H01L29/94

CPC分类号： H03F1/56 ,  G11C7/06 ,  H01L27/0811 ,  H01L29/7391 ,  H03F2200/183

摘要： A circuit comprises a control line and a two terminal semiconductor device having first and second terminals. The first terminal is coupled to a signal line, and the second terminal is coupled to the control line. The two terminal semiconductor device is adapted to have a capacitance when a voltage on the first terminal relative to the second terminal is above a threshold voltage and to have a smaller capacitance when a voltage on the first terminal relative to the second terminal is below the threshold voltage. The control line is coupled to a control signal and the signal line is coupled to a signal and is output of the circuit. A signal is placed on the signal line and voltage on the control line is modified (e.g., raised in the case of n-type devices, or lowered for a p-type devices). When the signal falls below the threshold voltage, the two terminal semiconductor device acts as a very small capacitor and the output of the circuit will be a small value. When the signal is above the threshold voltage, the two terminal semiconductor device acts as a large capacitor and the output of the circuit will be influenced by both the value of the signal and the value of the modified voltage on the control line and therefore the signal will be amplified.

摘要翻译： 电路包括控制线和具有第一和第二端子的两端子半导体器件。 第一端子耦合到信号线，并且第二端子耦合到控制线。 当第一端子上相对于第二端子的电压高于阈值电压时，两端子半导体器件适于具有电容，并且当第一端子上相对于第二端子的电压低于阈值时具有较小的电容 电压。 控制线耦合到控制信号，并且信号线耦合到信号并且是电路的输出。 将信号放置在信号线上，并且控制线上的电压被修改（例如在n型器件的情况下升高，或者对于p型器件降低）。 当信号低于阈值电压时，两端子半导体器件作为一个非常小的电容器，并且电路的输出将是一个小的值。 当信号高于阈值电压时，两端子半导体器件用作大电容器，电路的输出将受到信号值和控制线上修改电压值的影响，因此信号 将被放大。

公开(公告)号：US20050073871A1

公开(公告)日：2005-04-07

申请号：US10680348

申请日：2003-10-07

申请人： Wing Luk ,  Robert Dennard

发明人： Wing Luk ,  Robert Dennard

IPC分类号： G11C11/405 ,  H01L27/108 ,  G11C11/24

CPC分类号： H01L27/108 ,  G11C11/405

摘要： A random access memory (RAM) circuit is coupled to a write control line, a read control line, and one or more bitlines, and includes a write switch having a control terminal and first and second terminals. The first terminal of the write switch is coupled to the one or more bitlines, and the control terminal of the write switch is coupled to the write control line. The circuit includes a charge-storage device having first and second terminals, wherein a first terminal of the charge-storage device is coupled to the second terminal of the write switch and a second terminal of the charge-storage device is coupled to the read control line. The circuit includes a read switch having a control terminal and first and second terminals. The control terminal of the read switch is coupled to the first terminal of the charge-storage device and is coupled to the second terminal of the write switch. The first terminal of the read switch is coupled to the one or more bitlines, and the second terminal of the read switch coupled to ground. The circuit may be implemented through a number of disclosed semiconductor memory devices.

摘要翻译： 随机存取存储器（RAM）电路耦合到写入控制线，读取控制线和一个或多个位线，并且包括具有控制端子和第一和第二端子的写入开关。 写开关的第一端耦合到一个或多个位线，并且写开关的控制端耦合到写控制线。 该电路包括具有第一和第二端子的电荷存储装置，其中电荷存储装置的第一端子耦合到写入开关的第二端子，并且电荷存储装置的第二端子耦合到读取控制 线。 电路包括具有控制端子和第一和第二端子的读取开关。 读开关的控制端耦合到电荷存储装置的第一端并耦合到写开关的第二端。 读开关的第一端耦合到一个或多个位线，并且读开关的第二端耦合到地。 电路可以通过许多公开的半导体存储器件实现。

公开(公告)号：US20050128803A1

公开(公告)日：2005-06-16

申请号：US10735061

申请日：2003-12-11

申请人： Wing Luk ,  Robert Dennard

发明人： Wing Luk ,  Robert Dennard

IPC分类号： H01L27/108 ,  G11C11/36 ,  G11C11/401 ,  G11C11/405 ,  G11C11/409 ,  H01L21/8242

CPC分类号： G11C11/405

摘要： A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”).

摘要翻译： 提供了门控二极管存储单元，其包括一个或多个晶体管，例如场效应晶体管（“FET”），以及与FET信号通信的门控二极管，使得门控二极管的栅极与源极信号通信 第一FET的栅极，其中栅极二极管的栅极形成存储单元的一个端子，门控二极管的源极形成存储单元的另一个端子，第一FET的漏极与位线（“BL” “），并且第一FET的栅极与写入字线（”WLw“）进行信号通信，并且门控二极管的源极与读取字线（”WLr“）进行信号通信。

公开(公告)号：US20050030817A1

公开(公告)日：2005-02-10

申请号：US10635331

申请日：2003-08-06

申请人： Wing Luk ,  Robert Dennard ,  Stephen Kosonocky

发明人： Wing Luk ,  Robert Dennard ,  Stephen Kosonocky

IPC分类号： G11C5/06 ,  G11C11/406 ,  G11C11/4074 ,  G11C5/00

CPC分类号： G11C5/063 ,  G11C11/406 ,  G11C11/4074 ,  G11C2207/104

摘要： An integrated circuit, such as a memory macro, includes multiple power rails supporting first and second voltage differentials, with the second voltage differential being smaller than the first voltage differential. Signal lines in the integrated circuit are driven with the small voltage swing, which is generated by small swing circuits. The integrated circuit further includes regeneration circuits, which are receiving small voltage swing inputs and are outputting first, or full voltage swings. The application of the small voltage swing to the signal lines saves power in the integrated circuit. A wide bandwidth, full-wordline I/O, memory integrated circuit has simultaneously operable connection paths between essentially all the memory cells that are attached to the same wordline and the corresponding I/O terminals, and it has a single ended data-line structure.

摘要翻译： 诸如存储器宏的集成电路包括支持第一和第二电压差的多个电源轨，第二电压差小于第一电压差。 集成电路中的信号线由小的摆动电路产生的小电压摆动驱动。 集成电路还包括正在接收小电压摆幅输入并且正在输出第一或全电压摆幅的再生电路。 将小电压摆幅应用于信号线节省了集成电路中的功率。 宽带宽全字I / O存储器集成电路具有在连接到相同字线和对应的I / O端子的基本上所有存储单元之间的同时可操作的连接路径，并且具有单端数据线结构 。