公开(公告)号：US06373103B1

公开(公告)日：2002-04-16

申请号：US09541124

申请日：2000-03-31

申请人： Wei Long ,  Qi Xiang ,  Yowjuang W. Liu

发明人： Wei Long ,  Qi Xiang ,  Yowjuang W. Liu

IPC分类号： H01L2701

CPC分类号： H01L29/78624 ,  H01L29/41733 ,  H01L29/78612

摘要： A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.

摘要翻译： 半导体器件包括具有源极，主体和漏极区域的半导体层的晶片。 半导体区域的导电区域与源极区域和体区域重叠并电耦合。 源极和体区的电耦合减少了半导体器件中的浮体效应。 构造半导体器件的方法利用间隔物，掩模和/或倾斜注入来形成与半导体层的源极和体区域重叠的源极体导电区域，以及位于半导体器件的内部的漏极导电区域 漏极区域。

公开(公告)号：US06525381B1

公开(公告)日：2003-02-25

申请号：US09541127

申请日：2000-03-31

申请人： Wei Long ,  Qi Xiang ,  Yowjuang W. Liu

发明人： Wei Long ,  Qi Xiang ,  Yowjuang W. Liu

IPC分类号： H01L2976

CPC分类号： H01L29/66772 ,  H01L29/41733 ,  H01L29/78612 ,  H01L29/78624

摘要： A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.

摘要翻译： 半导体器件包括具有源极，主体和漏极区域的半导体层的晶片。 半导体区域的导电区域与源极区域和体区域重叠并电耦合。 源极和体区的电耦合减少了半导体器件中的浮体效应。 构造半导体器件的方法利用间隔物，掩模和/或倾斜注入来形成与半导体层的源极和体区域重叠的源极体导电区域，以及位于半导体器件的内部的漏极导电区域 漏极区域。

公开(公告)号：US06790750B1

公开(公告)日：2004-09-14

申请号：US10163676

申请日：2002-06-06

申请人： Wei Long ,  Qi Xiang ,  Yowjuang W. Liu

发明人： Wei Long ,  Qi Xiang ,  Yowjuang W. Liu

IPC分类号： H01L21425

CPC分类号： H01L29/66772 ,  H01L29/458 ,  H01L29/78612 ,  H01L29/78624

摘要： A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.

摘要翻译： 半导体器件包括具有源极，主体和漏极区域的半导体层的晶片。 半导体区域的导电区域与源极区域和体区域重叠并电耦合。 源极和体区的电耦合减少了半导体器件中的浮体效应。 构造半导体器件的方法利用间隔物，掩模和/或倾斜注入来形成与半导体层的源极和体区域重叠的源极体导电区域，以及位于半导体器件的内部的漏极导电区域 漏极区域。

公开(公告)号：US6153534A

公开(公告)日：2000-11-28

申请号：US361826

申请日：1999-07-27

申请人： Wei Long ,  Qi Xiang ,  Yowjuang W. Liu

发明人： Wei Long ,  Qi Xiang ,  Yowjuang W. Liu

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/49 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L29/66659 ,  H01L21/28105 ,  H01L21/2815 ,  H01L29/1054 ,  H01L29/4983 ,  H01L21/2807

摘要： A dual material gate is effectively fabricated for a field effect transistor having a short channel length of submicron and nanometer dimensions such that disadvantageous short channel effects are minimized. Generally, the method of the present invention includes a step of forming a first material gate portion on a gate dielectric. The first material gate portion has a source side and a drain side, and an aspect of the present invention further includes the step of depositing a spacer dielectric layer on the source side and the drain side of the first material gate portion. An aspect of the present invention also includes the step of implanting heavy ions into the spacer dielectric layer at an angle such that the spacer dielectric layer at the drain side of the first material gate portion is substantially not implanted with the heavy ions. The spacer dielectric layer is then selectively etched such that any portion of the spacer dielectric layer that is implanted with the heavy ions is etched. Thus, the spacer dielectric layer on the drain side of the first material gate portion is not etched, but the spacer dielectric layer on the source side of the first material gate portion is etched. In addition, an aspect of the present invention includes a step of selectively growing a second material gate portion from the first material gate portion that is exposed on the source side of the first material gate portion. In this manner, the dual material gate of the field effect transistor is comprised of the first material gate portion toward the drain of the field effect transistor and the second material gate portion toward the source of the field effect transistor.

摘要翻译： 对于具有亚微米和纳米尺寸的短沟道长度的场效应晶体管有效地制造双材料栅极，使得不利的短沟道效应最小化。 通常，本发明的方法包括在栅极电介质上形成第一材料栅极部分的步骤。 第一材料栅极部分具有源极侧和漏极侧，并且本发明的一个方面还包括在第一材料栅极部分的源极侧和漏极侧上沉积间隔电介质层的步骤。 本发明的一个方面还包括以一定角度将重离子注入到间隔电介质层中的步骤，使得第一材料栅极部分的漏极侧的间隔电介质层基本上不被重离子注入。 然后选择性地蚀刻间隔电介质层，使得蚀刻注入了重离子的间隔电介质层的任何部分。 因此，第一材料栅极部分的漏极侧的间隔物电介质层未被蚀刻，而是蚀刻第一材料栅极部分的源极侧的间隔物电介质层。 此外，本发明的一个方面包括从第一材料栅极部分选择性地生长第二材料栅极部分的步骤，该第一材料栅极部分暴露在第一材料栅极部分的源极侧。 以这种方式，场效应晶体管的双材料栅极包括朝向场效应晶体管的漏极的第一材料栅极部分和朝向场效应晶体管的源极的第二材料栅极部分。

公开(公告)号：US06441434B1

公开(公告)日：2002-08-27

申请号：US09541126

申请日：2000-03-31

申请人： Wei Long ,  Qi Xiang ,  Yowjuang W. Liu

发明人： Wei Long ,  Qi Xiang ,  Yowjuang W. Liu

IPC分类号： H01L2701

CPC分类号： H01L29/66772 ,  H01L29/458 ,  H01L29/78612 ,  H01L29/78624

摘要： A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.

摘要翻译： 半导体器件包括具有源极，主体和漏极区域的半导体层的晶片。 半导体区域的导电区域与源极区域和体区域重叠并电耦合。 源极和体区的电耦合减少了半导体器件中的浮体效应。 构造半导体器件的方法利用间隔物，掩模和/或倾斜注入来形成与半导体层的源极和体区域重叠的源极体导电区域，以及位于半导体器件的内部的漏极导电区域 漏极区域。

公开(公告)号：US06169302A

公开(公告)日：2001-01-02

申请号：US09361698

申请日：1999-07-27

申请人： Wei Long ,  Qi Xiang ,  Yowjuang W. Liu

发明人： Wei Long ,  Qi Xiang ,  Yowjuang W. Liu

IPC分类号： H01L2358

CPC分类号： H01L22/34 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention accurately determines a first parasitic capacitance component between a conductive gate region to a drain local interconnect of a real field effect transistor, and determines a second parasitic capacitance component between the conductive gate region to a source local interconnect of the real field effect transistor. A virtual field effect transistor is fabricated on a dielectric in order to determine the parasitic capacitance component between just the gate and the drain or source local interconnect of the real field effect transistor. The virtual field effect transistor includes a virtual drain local interconnect, a virtual source local interconnect, and a virtual conductive gate region fabricated on the dielectric with a respective size and positions relative to each other that are substantially the same as that of the drain and source local interconnects and the gate, respectively, of the real field effect transistor. In this manner, the first parasitic capacitance component between the conductive gate region of the real field effect transistor to the drain local interconnect of the real field effect transistor is a first capacitance measured between the virtual conductive gate region and the virtual drain local interconnect of the virtual field effect transistor of the present invention. Similarly, the second parasitic capacitance component between the conductive gate region of the real field effect transistor to the source local interconnect of the real field effect transistor is a second capacitance measured between the virtual conductive gate region and the virtual source local interconnect of the virtual field effect transistor of the present invention.

摘要翻译： 本发明精确地确定实际场效应晶体管的导电栅极与漏极局部互连之间的第一寄生电容分量，并且确定导电栅区与实场效应晶体管的源局部互连之间的第二寄生电容分量 。 在电介质上制造虚拟场效应晶体管，以便确定真实场效应晶体管的栅极和漏极或源局部互连之间的寄生电容分量。 虚拟场效应晶体管包括虚拟漏极局部互连，虚拟源局部互连和在电介质上制造的虚拟导电栅极区域，该虚拟导电栅极区域具有与漏极和源极基本上相同的尺寸和位置 分别是实际场效应晶体管的局部互连和栅极。 以这种方式，实际场效应晶体管的导电栅极区域与实场效应晶体管的漏极局部互连之间的第一寄生电容分量是在虚拟导电栅极区域和虚拟漏极局部互连之间测量的第一电容 虚拟场效应晶体管。 类似地，实场效应晶体管的导电栅极区域与实场效应晶体管的源局部互连之间的第二寄生电容分量是在虚拟导电栅极区域和虚拟场虚拟源局部互连之间测量的第二电容 效应晶体管。

公开(公告)号：US06275972B1

公开(公告)日：2001-08-14

申请号：US09310806

申请日：1999-05-12

申请人： Wei Long ,  Yowjuang W. Liu

发明人： Wei Long ,  Yowjuang W. Liu

IPC分类号： G06F1750

CPC分类号： H01L22/12 ,  G01R31/2621

摘要： A method for extracting a channel length between a source and a drain in a substrate of a transistor is disclosed herein. The method includes forward biasing the source with respect to the substrate to inject a charge into the substrate, collecting the charge at the drain, and calculating the channel length from the charge collected at the drain.

摘要翻译： 本文公开了一种在晶体管的衬底中提取源极和漏极之间的沟道长度的方法。 该方法包括相对于衬底向源偏置源，以将电荷注入到衬底中，在漏极处收集电荷，以及从在漏极处收集的电荷计算沟道长度。

公开(公告)号：US6069485A

公开(公告)日：2000-05-30

申请号：US237539

申请日：1999-01-26

申请人： Wei Long ,  Yowjuang W. Liu ,  Chun Jiang

发明人： Wei Long ,  Yowjuang W. Liu ,  Chun Jiang

IPC分类号： G01N27/22 ,  H01L21/66 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/1045 ,  G01N27/221 ,  H01L22/14

摘要： A method and apparatus that uses gate-to-substrate capacitance with varying amounts of source/drain junction bias to measure channel lateral doping profile by applying a series of different voltages between the source/drain and the substrate. The gate capacitance is measured for the different voltages. The capacitance is used to calculate the depletion width. From the depletion width, channel doping is calculated. Using this method direct evidence of a localized Boron pile up at source/drain edge is shown.

摘要翻译： 一种使用具有不同量的源极/漏极结偏置的栅极至衬底电容以通过在源极/漏极和衬底之间施加一系列不同电压来测量沟道横向掺杂分布的方法和装置。 对不同的电压测量栅极电容。 电容用于计算耗尽宽度。 从耗尽宽度，计算通道掺杂。 使用这种方法显示了在源极/漏极边缘处的局部硼堆积的直接证据。

公开(公告)号：US6166558A

公开(公告)日：2000-12-26

申请号：US237540

申请日：1999-01-26

申请人： Chun Jiang ,  Wei Long ,  Zicheng G. Ling ,  Yowjuang W. Liu

发明人： Chun Jiang ,  Wei Long ,  Zicheng G. Ling ,  Yowjuang W. Liu

IPC分类号： H01L21/66 ,  H01L29/78

CPC分类号： H01L22/12

摘要： The invention provides a method and apparatus for calculating gate length and source/drain gate overlap, by measuring gate capacitance. The invention uses previously known fringe capacitance C.sub.fr and unit capacitance C.sub.OX. The invention measures gate capacitance C.sub.g, when the gate is accumulatively biased, and solves for overlap capacitance C.sub.OV using the equation C.sub.OV =(C.sub.g -2C.sub.fr)/2 or C.sub.OV =(C.sub.gg -C.sub.gb -2C.sub.fr)/2. The invention then measures the gate capacitance C.sub.g when the gate to source/drain voltage is set to inversion bias and a zero voltage is applied between the source/drain and the substrate, and solves for the channel capacitance C.sub.ch using the equation C.sub.ch =C.sub.g -2C.sub.fr -2C.sub.OV. The invention calculates the channel capacitance C.sub.ch where C.sub.ch =C.sub.g -2C.sub.fr -2C.sub.OV and then calculates gate length where gate length L.sub.g =(2C.sub.OV +C.sub.ch)/C.sub.OX and the effective gate length L.sub.eff =C.sub.ch /C.sub.OX. The invention further calculates source/drain gate overlap L.sub.OV, by setting L.sub.OV =C.sub.OV /C.sub.OX.

摘要翻译： 本发明提供了一种通过测量栅极电容来计算栅极长度和源极/漏极栅极重叠的方法和装置。 本发明使用先前已知的边缘电容Cfr和单位电容COX。 本发明在栅极被累积偏置时测量栅极电容Cg，并使用公式COV =（Cg-2Cfr）/ 2或COV =（Cgg-Cgb-2Cfr）/ 2求解重叠电容COV。 然后，当栅极/源极/漏极电压被设置为反向偏压并且在源极/漏极和衬底之间施加零电压，并且使用公式Cch = Cg-1求解沟道电容Cch时，本发明测量栅极电容Cg。 2Cfr-2COV。 本发明计算Cch = Cg-2Cfr-2COV的沟道电容Cch，然后计算栅极长度Lg =（2COV + Cch）/ COX和有效栅极长度Leff = Cch / COX的栅极长度。 本发明通过设定LOV = COV / COX，进一步计算源极/漏极栅极重叠LOV。

公开(公告)号：US06232632B1

公开(公告)日：2001-05-15

申请号：US09436503

申请日：1999-11-09

申请人： Yowjuang W. Liu

发明人： Yowjuang W. Liu

IPC分类号： H01L29788

CPC分类号： H01L27/11553 ,  H01L27/115

摘要： Double density non-volatile memory cells having a trench structure are formed in a substrate, thereby facilitating miniaturization, improved planarization and low power programming and erasing. Each double density cell comprises two floating gates and a common control gate. Each pair of double density cells shares a common source region. Embodiments include forming first and second trenches in a substrate and depositing a tunnel dielectric layer in each trench. Polycrystalline silicon is then deposited filling each trench and a hole is etched forming two floating gate electrodes in each trench. An interpoly dielectric layer is then formed and a substantially T-shaped control gate electrode is deposited filling the hole between the floating gates and extending on the substrate.

摘要翻译： 在衬底中形成具有沟槽结构的双重密度非易失性存储单元，从而便于小型化，改进的平面化和低功率编程和擦除。 每个双密度单元包括两个浮动栅极和公共控制栅极。 每对双密度细胞共享一个共同的源区。 实施例包括在衬底中形成第一和第二沟槽，并在每个沟槽中沉积隧道介电层。 然后沉积多晶硅填充每个沟槽，并且蚀刻孔，在每个沟槽中形成两个浮置栅电极。 然后形成间隔电介质层，并且沉积基本上T形的控制栅极，填充浮置栅极之间的孔并在衬底上延伸。