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    Nitride semiconductor device
    1.
    发明授权
    Nitride semiconductor device 失效
    氮化物半导体器件

    公开(公告)号：US07329909B2

    公开(公告)日：2008-02-12

    申请号：US11149208

    申请日：2005-06-10

    Applicant: Wataru Saito ,  Ichiro Omura ,  Kouhei Morizuka

    Inventor： Wataru Saito ,  Ichiro Omura ,  Kouhei Morizuka

    IPC: H01L31/00

    CPC classification number: H01L29/7787 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/66462

    Abstract: A multi-layered structure in which a p-3C-SiC layer 102 is formed above a p-Si substrate 101 is formed, above which an I-GaN layer (channel layer) 103, an n-AlGaN layer (barrier layer) 104 are formed. A source electrode 201, a drain electrode 202, and a gate electrode 203 are formed above the n-AlGaN layer 104. The source electrode 201 and the drain electrode 202 form an ohmic contact with the n-AlGaN layer 104. The gate electrode 203 forms a Schottky junction with the n-AlGaN layer 104.

    Abstract translation: 形成在p-Si衬底101上形成p-3C-SiC层102的多层结构，其中I-GaN层（沟道层）103，n-AlGaN层（势垒层）104 形成。 源极电极201，漏极电极202和栅电极203形成在n-AlGaN层104的上方。 源电极201和漏电极202与n-AlGaN层104形成欧姆接触。 栅电极203与n-AlGaN层104形成肖特基结。

    Nitride semiconductor device
    2.
    发明申请
    Nitride semiconductor device 失效
    氮化物半导体器件

    公开(公告)号：US20060170003A1

    公开(公告)日：2006-08-03

    申请号：US11149208

    申请日：2005-06-10

    Applicant: Wataru Saito ,  Ichiro Omura ,  Kouhei Morizuka

    Inventor： Wataru Saito ,  Ichiro Omura ,  Kouhei Morizuka

    IPC: H01L31/109

    CPC classification number: H01L29/7787 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/66462

    Abstract: A multi-layered structure in which a p-3C-SiC layer 102 is formed above a p-Si substrate 101 is formed, above which an I-GaN layer (channel layer) 103, an n-AlGaN layer (barrier layer) 104 are formed. A source electrode 201, a drain electrode 202, and a gate electrode 203 are formed above the n-AlGaN layer 104. The source electrode 201 and the drain electrode 202 form an ohmic contact with the n-AlGaN layer 104. The gate electrode 203 forms a Schottky junction with the n-AlGaN layer 104.

    Abstract translation: 形成在p-Si衬底101上形成p-3C-SiC层102的多层结构，其中I-GaN层（沟道层）103，n-AlGaN层（势垒层）104 形成。 源极电极201，漏极电极202和栅电极203形成在n-AlGaN层104的上方。 源电极201和漏电极202与n-AlGaN层104形成欧姆接触。 栅电极203与n-AlGaN层104形成肖特基结。

    NITRIDE SEMICONDUCTOR DEVICE
    6.
    发明申请
    NITRIDE SEMICONDUCTOR DEVICE 失效
    氮化物半导体器件

    公开(公告)号：US20070241337A1

    公开(公告)日：2007-10-18

    申请号：US11766484

    申请日：2007-06-21

    Applicant: Wataru Saito ,  Ichiro Omura

    Inventor： Wataru Saito ,  Ichiro Omura

    IPC: H01L29/94

    CPC classification number: H01L29/66462 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/7786

    Abstract: In a nitride semiconductor device according to one embodiment of the invention, a p-type gallium nitride (GaN) layer electrically connected to a source electrode and extending and projecting to a drain electrode side with respect to a gate electrode is formed on an undoped or n-type aluminum gallium nitride (AlGaN) layer serving as a barrier layer.

    Abstract translation: 在根据本发明的一个实施方案的氮化物半导体器件中，在未掺杂的或未掺杂的或未掺杂的氮化物半导体器件上形成电连接到源电极并相对于栅电极延伸并突出到漏极侧的p型氮化镓（GaN） n型氮化镓铝（AlGaN）层作为阻挡层。

    Power semiconductor device
    7.
    发明授权
    Power semiconductor device 有权
    功率半导体器件

    公开(公告)号：US07276773B2

    公开(公告)日：2007-10-02

    申请号：US11117342

    申请日：2005-04-29

    Applicant: Wataru Saito ,  Ichiro Omura

    Inventor： Wataru Saito ,  Ichiro Omura

    IPC: H01L29/72

    CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0878 ,  H01L29/7397 ,  H01L29/872

    Abstract: A power semiconductor device includes second semiconductor layers of a first conductivity type and third semiconductor layers of a second conductivity type alternately disposed on a first semiconductor layer of the first conductivity type. The device further includes fourth semiconductor layers of the second conductivity type disposed in contact with upper portions of the third semiconductor layers between the second semiconductor layers, and fifth semiconductor layers of the first conductivity type formed in surfaces of the fourth semiconductor layers. The first semiconductor layer is lower in impurity concentration of the first conductivity type than each second semiconductor layer. The third semiconductor layer includes a fundamental portion and an impurity-amount-larger portion formed locally in a depth direction and higher in impurity amount than the fundamental portion. The impurity amount is defined by a total amount of impurities of the second conductivity type over a cross section in a lateral direction.

    Abstract translation: 功率半导体器件包括交替设置在第一导电类型的第一半导体层上的第一导电类型的第二半导体层和第二导电类型的第三半导体层。 该器件还包括第二导电类型的第四半导体层，与第二半导体层之间的第三半导体层的上部接触，以及形成在第四半导体层的表面中的第一导电类型的第五半导体层。 第一半导体层的第一导电类型的杂质浓度比每个第二半导体层低。 第三半导体层包括基本部分和在深度方向上局部形成的杂质量较大部分，并且杂质量高于基本部分。 杂质量由横向横截面上的第二导电类型的杂质的总量限定。

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20070114602A1

    公开(公告)日：2007-05-24

    申请号：US11562708

    申请日：2006-11-22

    Applicant: Wataru Saito ,  Ichiro Omura

    Inventor： Wataru Saito ,  Ichiro Omura

    IPC: H01L29/94

    CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811

    Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a first semiconductor region of the first conductivity type and a second semiconductor region of a second conductivity type alternately arranged in a lateral direction on the first semiconductor layer of the first conductivity type; a third semiconductor region of the second conductivity type formed on the first semiconductor region; a fourth semiconductor region of the first conductivity type formed on a portion of the surface of the third semiconductor region; a control electrode provided via an first insulating film in a groove formed in contact with the fourth semiconductor region, the third semiconductor region, and the first semiconductor region; a first main electrode electrically connected to the first semiconductor layer; a second main electrode forming a junction with the third and fourth semiconductor region; and a fifth semiconductor region of the second conductivity type. The fifth semiconductor region is formed in contact with the first insulating film, the first semiconductor region, and the second semiconductor region. The bottom face of the fifth semiconductor region is deeper than the bottom face of the control electrode. Alternatively, the fifth semiconductor region may be spaced apart from the first insulating film.

    Abstract translation: 半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第一半导体区域和在第一导电类型的第一半导体层上沿横向交替布置的第二导电类型的第二半导体区域; 形成在第一半导体区域上的第二导电类型的第三半导体区域; 形成在第三半导体区域的表面的一部分上的第一导电类型的第四半导体区域; 在与所述第四半导体区域，所述第三半导体区域和所述第一半导体区域接触形成的沟槽中经由第一绝缘膜设置的控制电极; 电连接到第一半导体层的第一主电极; 形成与第三和第四半导体区域的结的第二主电极; 和第二导电类型的第五半导体区域。 第五半导体区域形成为与第一绝缘膜，第一半导体区域和第二半导体区域接触。 第五半导体区域的底面比控制电极的底面更深。 或者，第五半导体区域可以与第一绝缘膜间隔开。

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