公开(公告)号：US07329909B2

公开(公告)日：2008-02-12

申请号：US11149208

申请日：2005-06-10

Applicant: Wataru Saito ,  Ichiro Omura ,  Kouhei Morizuka

Inventor： Wataru Saito ,  Ichiro Omura ,  Kouhei Morizuka

IPC: H01L31/00

CPC classification number: H01L29/7787 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/66462

Abstract: A multi-layered structure in which a p-3C-SiC layer 102 is formed above a p-Si substrate 101 is formed, above which an I-GaN layer (channel layer) 103, an n-AlGaN layer (barrier layer) 104 are formed. A source electrode 201, a drain electrode 202, and a gate electrode 203 are formed above the n-AlGaN layer 104. The source electrode 201 and the drain electrode 202 form an ohmic contact with the n-AlGaN layer 104. The gate electrode 203 forms a Schottky junction with the n-AlGaN layer 104.

Abstract translation: 形成在p-Si衬底101上形成p-3C-SiC层102的多层结构，其中I-GaN层（沟道层）103，n-AlGaN层（势垒层）104 形成。 源极电极201，漏极电极202和栅电极203形成在n-AlGaN层104的上方。 源电极201和漏电极202与n-AlGaN层104形成欧姆接触。 栅电极203与n-AlGaN层104形成肖特基结。

公开(公告)号：US20060170003A1

公开(公告)日：2006-08-03

申请号：US11149208

申请日：2005-06-10

Applicant: Wataru Saito ,  Ichiro Omura ,  Kouhei Morizuka

Inventor： Wataru Saito ,  Ichiro Omura ,  Kouhei Morizuka

IPC: H01L31/109

CPC classification number: H01L29/7787 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/66462

Abstract: A multi-layered structure in which a p-3C-SiC layer 102 is formed above a p-Si substrate 101 is formed, above which an I-GaN layer (channel layer) 103, an n-AlGaN layer (barrier layer) 104 are formed. A source electrode 201, a drain electrode 202, and a gate electrode 203 are formed above the n-AlGaN layer 104. The source electrode 201 and the drain electrode 202 form an ohmic contact with the n-AlGaN layer 104. The gate electrode 203 forms a Schottky junction with the n-AlGaN layer 104.

Abstract translation: 形成在p-Si衬底101上形成p-3C-SiC层102的多层结构，其中I-GaN层（沟道层）103，n-AlGaN层（势垒层）104 形成。 源极电极201，漏极电极202和栅电极203形成在n-AlGaN层104的上方。 源电极201和漏电极202与n-AlGaN层104形成欧姆接触。 栅电极203与n-AlGaN层104形成肖特基结。

公开(公告)号：US07317225B2

公开(公告)日：2008-01-08

申请号：US11551526

申请日：2006-10-20

Applicant: Wataru Saito ,  Ichiro Omura

Inventor： Wataru Saito ,  Ichiro Omura

IPC: H01L29/76

CPC classification number: H01L29/66712 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/7811

Abstract: The power semiconductor device according to one embodiment of the present invention at least comprises: first pillar layers of the first conductive type and second pillar layers of a second conductive type which constitute a super-junction structure in a device section and which are arranged alternately in a horizontal direction, each of the first and second pillar layers having a column-shaped sectional structure; third pillar layers of the first conductive type and fourth pillar layers of the second conductive type which are adjacent to the super-junction structure of the device section to constitute another super-junction structure thinner in a vertical direction than the super-junction structure of the device section in a device termination section and which are arranged alternately in a horizontal direction, each of the third and fourth pillar layers having a column-shaped sectional structure; an outermost pillar layer which is stacked on one of the third or fourth pillar layers in the super-junction structure of the device termination section nearest to the device section to be additionally formed to an outermost portion of the super-junction structure of the device section nearest to the device termination section and which has an impurity concentration less than that of each of the first and second pillar layers; a high resistance layer of the first conductive type which is formed on the third pillar layers and the fourth pillar layers and has a resistance value higher than that of each of the first and second pillar layers.

Abstract translation: 根据本发明的一个实施例的功率半导体器件至少包括：第一导电类型的第一柱层和第二导电类型的第二柱层，其在器件部分中构成超结结构，并且交替布置在 水平方向，第一和第二柱层中的每一个具有柱状截面结构; 第二导电类型的第一导电类型和第四柱层的第三柱层与器件部分的超结结构相邻以构成在垂直方向上比第二导体类型的超结结构更薄的超结结构 装置部分，其在水平方向上交替布置，每个第三和第四柱层都具有柱状截面结构; 最外层柱层层叠在最靠近器件部分的器件端接部分的超结结构中的第三或第四柱层之一上，以附加地形成在器件部分的超结结构的最外部分 最靠近器件终止部分，其杂质浓度小于第一和第二柱层的杂质浓度; 所述第一导电类型的高电阻层形成在所述第三柱层和所述第四柱层上，并且具有高于所述第一和第二柱层中的每一个的电阻值。

公开(公告)号：US07238576B2

公开(公告)日：2007-07-03

申请号：US10403122

申请日：2003-04-01

Applicant: Masakazu Yamaguchi ,  Ichiro Omura ,  Wataru Saito ,  Takashi Shinohe ,  Hiromichi Ohashi

Inventor： Masakazu Yamaguchi ,  Ichiro Omura ,  Wataru Saito ,  Takashi Shinohe ,  Hiromichi Ohashi

IPC: H01L21/336

CPC classification number: H01L29/7803 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/66712 ,  H01L29/7722 ,  H01L29/7802 ,  H01L29/7805 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7824

Abstract: A semiconductor device comprises a drain layer of first conductivity type, drift layers of first and second conductivity types on the drain layer, an insulating film between the drift layers and contacting the drift layers, a first base layer of second conductivity type on a surface of the drift layer of first conductivity type, a source layer of first conductivity type selectively provided on a surface of the first base layer of second conductivity type, a gate insulating film on the first base layer of second conductivity type between the source layer and the drift layer, a gate electrode on the gate insulating film, a second base layer of second conductivity type on a surface of the drift layer, a first main electrode on the drain layer, and a second main electrode on the source layer, the first base layer and the second base layer.

Abstract translation: 半导体器件包括第一导电类型的漏极层，漏极层上的第一和第二导电类型的漂移层，漂移层之间的绝缘膜和与漂移层接触的第二导电类型的第一基底层， 第一导电类型的漂移层，选择性地设置在第二导电类型的第一基极层的表面上的第一导电类型的源极层，在源极层和漂移体之间的第二导电类型的第一基极层上的栅极绝缘膜 栅极绝缘膜上的栅电极，漂移层的表面上的第二导电类型的第二基极层，漏极层上的第一主电极和源极层上的第二主电极，第一基极层 和第二基层。

公开(公告)号：US07157748B2

公开(公告)日：2007-01-02

申请号：US11014866

申请日：2004-12-20

Applicant: Wataru Saito ,  Ichiro Omura

Inventor： Wataru Saito ,  Ichiro Omura

IPC: H01L31/00

CPC classification number: H01L29/7787 ,  H01L29/2003

Abstract: A nitride-based semiconductor device includes a first semiconductor layer consisting essentially of a nitride-based semiconductor, and a second semiconductor layer disposed on the first semiconductor layer and consisting essentially of a non-doped or first conductivity type nitride-based semiconductor. The first and second semiconductor layers forms a hetero-interface. A gate electrode is disposed on the second semiconductor layer. First and second trenches are formed in a surface of the second semiconductor layer at positions sandwiching the gate electrode. Third and fourth semiconductor layers of the first conductivity type are respectively formed in surfaces of the first and second trenches and each consist essentially of a diffusion layer having a resistivity lower than the first and second semiconductor layers. Source and drain electrodes are electrically connected to the third and fourth semiconductor layers, respectively.

Abstract translation: 氮化物基半导体器件包括基本上由氮化物基半导体组成的第一半导体层和设置在第一半导体层上并基本上由非掺杂或第一导电型氮化物基半导体构成的第二半导体层。 第一和第二半导体层形成异质界面。 栅电极设置在第二半导体层上。 第一和第二沟槽在夹着栅电极的位置处形成在第二半导体层的表面中。 第一导电类型的第三和第四半导体层分别形成在第一和第二沟槽的表面中，并且每个半导体层基本上由电阻率低于第一和第二半导体层的扩散层组成。 源电极和漏电极分别电连接到第三和第四半导体层。

公开(公告)号：US20060284248A1

公开(公告)日：2006-12-21

申请号：US11453997

申请日：2006-06-16

Applicant: Wataru Saito ,  Ichiro Omura

Inventor： Wataru Saito ,  Ichiro Omura

IPC: H01L29/76

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712

Abstract: First semiconductor pillar layers of a first conduction type and second semiconductor pillar layers of a second conduction type are arranged on a first semiconductor layer of the first conduction type laterally, periodically and alternately at a first period to forma first pillar layer. Third semiconductor pillar layers of the first conduction type and fourth semiconductor pillar layers of the second conduction type are arranged on the first pillar layer laterally, periodically and alternately at a second period smaller than the first period to form a second pillar layer. A semiconductor base layer of the second conduction type is formed on a surface of the fourth semiconductor pillar layer. A semiconductor diffused layer of the first conduction type is formed on a surface of the semiconductor base layer.

Abstract translation: 第一导电类型的第一半导体柱层和第二导电类型的第二半导体柱层被布置在第一导电类型的第一半导体层上，以第一周期方式，周期性地交替地布置以形成第一柱层。 第二导电类型的第一导电类型的第三半导体柱层和第二导电类型的第四半导体柱层在第一柱层上以比第一周期小的周期性地交替布置在第一柱层上，以形成第二柱层。 在第四半导体柱层的表面上形成第二导电类型的半导体基底层。 在半导体基底层的表面上形成第一导电类型的半导体扩散层。

公开(公告)号：US20060131644A1

公开(公告)日：2006-06-22

申请号：US11117342

申请日：2005-04-29

Applicant: Wataru Saito ,  Ichiro Omura

Inventor： Wataru Saito ,  Ichiro Omura

IPC: H01L31/113

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0878 ,  H01L29/7397 ,  H01L29/872

Abstract: A power semiconductor device includes second semiconductor layers of a first conductivity type and third semiconductor layers of a second conductivity type alternately disposed on a first semiconductor layer of the first conductivity type. The device further includes fourth semiconductor layers of the second conductivity type disposed in contact with upper portions of the third semiconductor layers between the second semiconductor layers, and fifth semiconductor layers of the first conductivity type formed in surfaces of the fourth semiconductor layers. The first semiconductor layer is lower in impurity concentration of the first conductivity type than each second semiconductor layer. The third semiconductor layer includes a fundamental portion and an impurity-amount-larger portion formed locally in a depth direction and higher in impurity amount than the fundamental portion. The impurity amount is defined by a total amount of impurities of the second conductivity type over a cross section in a lateral direction.

Abstract translation: 功率半导体器件包括交替设置在第一导电类型的第一半导体层上的第一导电类型的第二半导体层和第二导电类型的第三半导体层。 该器件还包括第二导电类型的第四半导体层，与第二半导体层之间的第三半导体层的上部接触，以及形成在第四半导体层的表面中的第一导电类型的第五半导体层。 第一半导体层的第一导电类型的杂质浓度比每个第二半导体层低。 第三半导体层包括基本部分和在深度方向上局部形成的杂质量较大部分，并且杂质量高于基本部分。 杂质量由横向横截面上的第二导电类型的杂质的总量限定。

公开(公告)号：US07049658B2

公开(公告)日：2006-05-23

申请号：US10602596

申请日：2003-06-25

Applicant: Wataru Saito ,  Ichiro Omura ,  Tsuneo Ogura

Inventor： Wataru Saito ,  Ichiro Omura ,  Tsuneo Ogura

IPC: H01L29/94

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/66712 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a power semiconductor device, including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type which are alternately and laterally arranged on the first semiconductor layer and, a fourth semiconductor layer of the second conductivity type selectively formed in the surface regions of the second and third semiconductor layers, a fifth semiconductor layer of the first conductivity type selectively formed in the surface region of the fourth semiconductor layer, and a control electrode formed on the surfaces of the second, fourth and fifth semiconductor layers, in which a layer thickness ratio A is given by the expression: 0

Abstract translation: 公开了一种功率半导体器件，包括第一导电类型的第一半导体层，第一导电类型的第二半导体层和第二导电类型的第三半导体层，其交替地和横向地布置在第一半导体层上， 选择性地形成在第二和第三半导体层的表面区域中的第二导电类型的第四半导体层，选择性地形成在第四半导体层的表面区域中的第一导电类型的第五半导体层和形成在第二半导体层上的控制电极 第二半导体层，第四半导体层和第五半导体层的表面，其中层厚度比A由以下表达式给出：<？in-line-formula description =“In-line Formulas”end =“lead”？> 0 其中t是第一半导体层的厚度，d是 第二次 d半导体层。

公开(公告)号：US20060054924A1

公开(公告)日：2006-03-16

申请号：US11014866

申请日：2004-12-20

Applicant: Wataru Saito ,  Ichiro Omura

Inventor： Wataru Saito ,  Ichiro Omura

IPC: H01L31/0328

CPC classification number: H01L29/7787 ,  H01L29/2003

Abstract: A nitride-based semiconductor device includes a first semiconductor layer consisting essentially of a nitride-based semiconductor, and a second semiconductor layer disposed on the first semiconductor layer and consisting essentially of a non-doped or first conductivity type nitride-based semiconductor. The first and second semiconductor layers forms a hetero-interface. A gate electrode is disposed on the second semiconductor layer. First and second trenches are formed in a surface of the second semiconductor layer at positions sandwiching the gate electrode. Third and fourth semiconductor layers of the first conductivity type are respectively formed in surfaces of the first and second trenches and each consist essentially of a diffusion layer having a resistivity lower than the first and second semiconductor layers. Source and drain electrodes are electrically connected to the third and fourth semiconductor layers, respectively.

Abstract translation: 氮化物基半导体器件包括基本上由氮化物基半导体组成的第一半导体层和设置在第一半导体层上并基本上由非掺杂或第一导电型氮化物基半导体构成的第二半导体层。 第一和第二半导体层形成异质界面。 栅电极设置在第二半导体层上。 第一和第二沟槽在夹着栅电极的位置处形成在第二半导体层的表面中。 第一导电类型的第三和第四半导体层分别形成在第一和第二沟槽的表面中，并且每个半导体层基本上由电阻率低于第一和第二半导体层的扩散层组成。 源电极和漏电极分别电连接到第三和第四半导体层。

公开(公告)号：US20060043501A1

公开(公告)日：2006-03-02

申请号：US11109858

申请日：2005-04-20

Applicant: Wataru Saito ,  Ichiro Omura

Inventor： Wataru Saito ,  Ichiro Omura

IPC: H01L29/76

CPC classification number: H01L29/66462 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/7786

Abstract: In a nitride semiconductor device according to one embodiment of the invention, a p-type gallium nitride (GaN) layer electrically connected to a source electrode and extending and projecting to a drain electrode side with respect to a gate electrode is formed on an undoped or n-type aluminum gallium nitride (AlGaN) layer serving as a barrier layer.

Abstract translation: 在根据本发明的一个实施方案的氮化物半导体器件中，在未掺杂的或未掺杂的或未掺杂的氮化物半导体器件上形成电连接到源电极并相对于栅电极延伸并突出到漏极侧的p型氮化镓（GaN） n型氮化镓铝（AlGaN）层作为阻挡层。