公开(公告)号：US11563012B2

公开(公告)日：2023-01-24

申请号：US17324114

申请日：2021-05-19

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Shih-Fang Tzou ,  Chien-Ting Ho ,  Ying-Chiao Wang ,  Yu-Ching Chen ,  Hui-Ling Chuang ,  Kuei-Hsuan Yu

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/762

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

公开(公告)号：US10672864B2

公开(公告)日：2020-06-02

申请号：US16297733

申请日：2019-03-11

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chin Wu ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Jui-Min Lee ,  Po-Chun Chen ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Wen-Chieh Lu ,  Chien-Ting Ho ,  Tsung-Ying Tsai ,  Kai-Ping Chen

IPC: H01L49/02 ,  H01L29/94 ,  H01L27/108

Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.

公开(公告)号：US10670958B2

公开(公告)日：2020-06-02

申请号：US15937825

申请日：2018-03-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Yu-Cheng Tung ,  Li-Wei Feng ,  Chien-Ting Ho

IPC: G03F1/36 ,  G03F7/20 ,  H01L27/108

Abstract: A method of forming a layout pattern is disclosed. First, an array comprising a plurality of main features is provided wherein the main features are arranged into a plurality of rows along a first direction and are parallel and staggered along a second direction. Assistant features are inserted into each row of the main features. A shortest distance d1 between the main features in row n to the main features in row n+1 and a shortest distance d2 between the main feature in row n−1 to the main feature in row n+1 are obtained. The assistance features inserted in row n of the main features are then adjusted according to the difference between the distances d1 and d2. After that, the main features and the assistant features are output to a photo mask.

公开(公告)号：US20190341252A1

公开(公告)日：2019-11-07

申请号：US15968680

申请日：2018-05-01

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ming-Te Wei ,  Yu-Chieh Lin ,  Ying-Chiao Wang ,  Chien-Ting Ho

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/02

Abstract: A method for patterning a semiconductor structure is provided, including forming an additional third material layer on a thinner portion of a second material layer to be an etching buffer layer. The removed thickness of the thinner portion of the second material layer covered by the third material layer during an etching back process is therefore reduced.

公开(公告)号：US20190206874A1

公开(公告)日：2019-07-04

申请号：US16294934

申请日：2019-03-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Li-Wei Feng ,  Chien-Ting Ho

IPC: H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/10805 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: A semiconductor memory device and a manufacturing method thereof are provided. At least one bit line structure including a first metal layer, a bit line capping layer, and a first silicon layer located between the first metal layer and the bit line capping layer is formed on a semiconductor substrate. A bit line contact opening penetrating the bit line capping layer is formed for exposing a part of the first silicon layer. A first metal silicide layer is formed on the first silicon layer exposed by the bit line contact opening. A bit line contact structure is formed in the bit line contact opening and contacts the first metal silicide layer for being electrically connected to the bit line structure. The first silicon layer in the bit line structure may be used to protect the first metal layer from being damaged by the process of forming the metal silicide layer.

公开(公告)号：US20180350817A1

公开(公告)日：2018-12-06

申请号：US16043166

申请日：2018-07-24

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Li-Wei Feng ,  Chien-Ting Ho ,  Wen-Chieh Lu ,  Li-Wei Liu

IPC: H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.

公开(公告)号：US20180335703A1

公开(公告)日：2018-11-22

申请号：US15937825

申请日：2018-03-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Yu-Cheng Tung ,  Li-Wei Feng ,  Chien-Ting Ho

IPC: G03F7/20 ,  G03F1/36 ,  G06F17/50

Abstract: A method of forming a layout pattern is disclosed. First, an array comprising a plurality of main features is provided wherein the main features are arranged into a plurality of rows along a first direction and are parallel and staggered along a second direction. Assistant features are inserted into each row of the main features. A shortest distance d1 between the main features in row n to the main features in row n+1 and a shortest distance d2 between the main feature in row n−1 to the main feature in row n+1 are obtained. The assistance features inserted in row n of the main features are then adjusted according to the difference between the distances d1 and d2. After that, the main features and the assistant features are output to a photo mask.

公开(公告)号：US20180308923A1

公开(公告)日：2018-10-25

申请号：US15927103

申请日：2018-03-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chin Wu ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Jui-Min Lee ,  Po-Chun Chen ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Wen-Chieh Lu ,  Chien-Ting Ho ,  Tsung-Ying Tsai ,  Kai-Ping Chen

IPC: H01L49/02 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L28/82 ,  H01L27/10808 ,  H01L27/10855 ,  H01L28/87 ,  H01L29/94

Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.

公开(公告)号：US20180226409A1

公开(公告)日：2018-08-09

申请号：US15884399

申请日：2018-01-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Li-Wei Feng ,  Chien-Ting Ho

IPC: H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/10805 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: A semiconductor memory device and a manufacturing method thereof are provided. At least one bit line structure including a first metal layer, a bit line capping layer, and a first silicon layer located between the first metal layer and the bit line capping layer is formed on a semiconductor substrate. A bit line contact opening penetrating the bit line capping layer is formed for exposing a part of the first silicon layer. A first metal silicide layer is formed on the first silicon layer exposed by the bit line contact opening. A bit line contact structure is formed in the bit line contact opening and contacts the first metal silicide layer for being electrically connected to the bit line structure. The first silicon layer in the bit line structure may be used to protect the first metal layer from being damaged by the process of forming the metal silicide layer.

公开(公告)号：US20170365675A1

公开(公告)日：2017-12-21

申请号：US15183800

申请日：2016-06-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yu Chang ,  Ying-Chiao Wang ,  Hon-Huei Liu ,  Jyh-Shyang Jenq ,  Chung-Liang Chu ,  Yu-Ruei Chen

IPC: H01L29/423 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/02

CPC classification number: H01L21/32139 ,  H01L27/0207

Abstract: A dummy pattern arrangement and a method of arranging dummy patterns are provided in the present invention. The dummy pattern arrangement includes a substrate with a dummy region, a plurality of first base dummy cells arranged spaced apart from each other along a first direction in the dummy region, and two first edge dummy cells arranged respectively at two opposite sides of the first base dummy cells along the first direction in the dummy region.