Invention Application
- Patent Title: METHOD FOR PATTERNING A SEMICONDUCTOR STRUCTURE
-
Application No.: US15968680Application Date: 2018-05-01
-
Publication No.: US20190341252A1Publication Date: 2019-11-07
- Inventor: Li-Wei Feng , Ming-Te Wei , Yu-Chieh Lin , Ying-Chiao Wang , Chien-Ting Ho
- Applicant: UNITED MICROELECTRONICS CORP. , Fujian Jinhua Integrated Circuit Co., Ltd.
- Main IPC: H01L21/033
- IPC: H01L21/033 ; H01L21/311 ; H01L21/02
Abstract:
A method for patterning a semiconductor structure is provided, including forming an additional third material layer on a thinner portion of a second material layer to be an etching buffer layer. The removed thickness of the thinner portion of the second material layer covered by the third material layer during an etching back process is therefore reduced.
Public/Granted literature
- US10475648B1 Method for patterning a semiconductor structure Public/Granted day:2019-11-12
Information query
IPC分类:
