公开(公告)号：US09711646B2

公开(公告)日：2017-07-18

申请号：US14230223

申请日：2014-03-31

Applicant: United Microelectronics Corp.

Inventor： Yu-Ping Wang ,  Jyh-Shyang Jenq ,  Yu-Hsiang Lin ,  Hsuan-Hsu Chen ,  Chien-Hao Chen ,  Yi-Han Ye

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.

公开(公告)号：US20140343880A1

公开(公告)日：2014-11-20

申请号：US13894021

申请日：2013-05-14

Applicant: United Microelectronics Corp.

Inventor： Yi-Ting Wu ,  Cheng-Tung Huang ,  Tsung-Han Lee ,  Yi-Han Ye

IPC: G06F17/11 ,  G01R19/00

CPC classification number: G01R19/0084 ,  G01R31/2621

Abstract: A method for deriving characteristic values of a MOS transistor is described. A set of ηk values is provided. A set of VBi values (i=1 to M, M≧3) is provided. A set of RSDi,j (i=1 to M−1, j=i+1 to M) values each under a pair of VBi and VBj, or a set of Vtq—q,j (q is one of 1 to M, j is 1 to M excluding q) values under VBq is derived for each ηk, with an iteration method. The ηk value making the set of RSDi,j values or Vtq—q,j values closest to each other is determined as an accurate ηk value. The mean value of RSDi,j at the accurate ηk value is calculated as an accurate RSD value.

Abstract translation: 描述用于导出MOS晶体管的特性值的方法。 提供了一组＆eegr k值。 提供一组VBi值（i = 1〜M，M≥3）。 一组RSDi，j（i = 1〜M-1，j = i + 1〜M）的值分别为一对VBi和VBj，或一组Vtq-q，j（q为1〜M ，j为1到M，不包括q）使用迭代方法为每个＆eegr k导出VBq下的值。 使得最接近的RSDi，j值或Vtq-q，j值的集合被确定为精确的k值。 RSDi，j在精确的k值的平均值被计算为准确的RSD值。

公开(公告)号：US11101384B1

公开(公告)日：2021-08-24

申请号：US17072064

申请日：2020-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zong-Han Lin ,  Yi-Han Ye

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06

Abstract: A power semiconductor device includes a substrate, a first well, a second well, a drain, a source, a first gate structure, a second gate structure and a doping region. The first well has a first conductivity and extends into the substrate from a substrate surface. The second well has a second conductivity and extends into the substrate from the substrate surface. The drain has the first conductivity and is disposed in the first well. The source has the first conductivity and is disposed in the second well. The first gate structure is disposed on the substrate surface and at least partially overlapping with the first well and second well. The second gate structure is disposed on the substrate surface and overlapping with the second well. The doping region has the first conductivity, is disposed in the second well and connects the first gate structure with the second gate structure.

公开(公告)号：US20150279957A1

公开(公告)日：2015-10-01

申请号：US14230223

申请日：2014-03-31

Applicant: United Microelectronics Corp.

Inventor： Yu-Ping Wang ,  Jyh-Shyang Jenq ,  Yu-Hsiang Lin ,  Hsuan-Hsu Chen ,  Chien-Hao Chen ,  Yi-Han Ye

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.

Abstract translation: 公开了一种半导体结构及其制造方法。 半导体结构包括第一栅极结构，第二栅极结构和第二电介质间隔物。 彼此相邻的第一栅极结构和第二栅极结构中的每一个包括第一电介质间隔物。 第二电介质间隔物位于第一栅极结构的相对侧壁中的一个上，而不设置在第二栅极结构的电介质间隔物上。

公开(公告)号：US09632115B2

公开(公告)日：2017-04-25

申请号：US13894021

申请日：2013-05-14

Applicant: United Microelectronics Corp.

Inventor： Yi-Ting Wu ,  Cheng-Tung Huang ,  Tsung-Han Lee ,  Yi-Han Ye

IPC: G01R19/00 ,  G01R31/26

CPC classification number: G01R19/0084 ,  G01R31/2621

Abstract: A method for deriving characteristic values of a MOS transistor is described. A set of ηk values is provided. A set of VBi values (i=1 to M, M≧3) is provided. A set of RSDi,j (i=1 to M−1, j=i+1 to M) values each under a pair of VBi and VBj, or a set of Vtq_q,j (q is one of 1 to M, j is 1 to M excluding q) values under VBq is derived for each ηk, with an iteration method. The ηk value making the set of RSDi,j values or Vtq_q,j values closest to each other is determined as an accurate ηk value. The mean value of RSDi,j at the accurate ηk value is calculated as an accurate RSD value.

公开(公告)号：US20220328684A1

公开(公告)日：2022-10-13

申请号：US17314069

申请日：2021-05-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zong-Han Lin ,  Yi-Han Ye

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

Abstract: A method for fabricating a lateral diffusion metal oxide semiconductor (LDMOS) device includes the steps of first forming a first fin-shaped structure and a second fin-shaped structure on a substrate, forming a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure, forming a first gate structure on the first fin-shaped structure and a second gate structure on the second fin-shaped structure, forming a source region on the first fin-shaped structure, forming a drain region on the second fin-shaped structure, and forming a contact field plate directly on the STI.

公开(公告)号：US08822297B2

公开(公告)日：2014-09-02

申请号：US13748279

申请日：2013-01-23

Applicant: United Microelectronics Corp.

Inventor： Tsung-Han Lee ,  Cheng-Tung Huang ,  Yi-Han Ye

IPC: H01L21/8249

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

Abstract: Provided is a method of fabricating a MOS device including the following steps. At least one gate structure is formed on a substrate, wherein the gate structure includes a gate conductive layer and a hard mask layer disposed on the gate conductive layer. A first implant process is performed to form source and drain extension regions in the substrate, wherein the gate conductive layer is covered by the hard mask layer. A process is of removing the hard mask layer is performed to expose the surface of the gate conductive layer. A second implant process is performed to form pocket doped regions in the substrate, wherein the gate conductive layer is not covered by the hard mask layer.

Abstract translation: 提供了一种制造MOS器件的方法，包括以下步骤。 在衬底上形成至少一个栅极结构，其中栅极结构包括栅极导电层和设置在栅极导电层上的硬掩模层。 执行第一注入工艺以在衬底中形成源极和漏极延伸区域，其中栅极导电层被硬掩模层覆盖。 执行去除硬掩模层以暴露栅极导电层的表面的工艺。 执行第二注入工艺以在衬底中形成口袋掺杂区域，其中栅极导电层未被硬掩模层覆盖。

公开(公告)号：US20140206170A1

公开(公告)日：2014-07-24

申请号：US13748279

申请日：2013-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Han Lee ,  Cheng-Tung Huang ,  Yi-Han Ye

IPC: H01L29/66

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

Abstract: Provided is a method of fabricating a MOS device including the following steps. At least one gate structure is formed on a substrate, wherein the gate structure includes a gate conductive layer and a hard mask layer disposed on the gate conductive layer. A first implant process is performed to form source and drain extension regions in the substrate, wherein the gate conductive layer is covered by the hard mask layer. A process is of removing the hard mask layer is performed to expose the surface of the gate conductive layer. A second implant process is performed to form pocket doped regions in the substrate, wherein the gate conductive layer is not covered by the hard mask layer.

Abstract translation: 提供了一种制造MOS器件的方法，包括以下步骤。 在衬底上形成至少一个栅极结构，其中栅极结构包括栅极导电层和设置在栅极导电层上的硬掩模层。 执行第一注入工艺以在衬底中形成源极和漏极延伸区域，其中栅极导电层被硬掩模层覆盖。 执行去除硬掩模层以暴露栅极导电层的表面的工艺。 执行第二注入工艺以在衬底中形成口袋掺杂区域，其中栅极导电层未被硬掩模层覆盖。

公开(公告)号：US20230238457A1

公开(公告)日：2023-07-27

申请号：US18128234

申请日：2023-03-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zong-Han Lin ,  Yi-Han Ye

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/66681 ,  H01L29/407

Abstract: A lateral diffusion metal oxide semiconductor (LDMOS) device includes a first fin-shaped structure on a substrate, a shallow trench isolation (STI) adjacent to the first fin-shaped structure, a first gate structure on the first fin-shaped structure, a spacer adjacent to the first gate structure, and a contact field plate adjacent to the first gate structure and directly on the STI. Preferably, a sidewall of the spacer is aligned with a sidewall of the first fin-shaped structure.

公开(公告)号：US11652168B2

公开(公告)日：2023-05-16

申请号：US17314069

申请日：2021-05-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zong-Han Lin ,  Yi-Han Ye

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/407 ,  H01L29/66681

Abstract: A method for fabricating a lateral diffusion metal oxide semiconductor (LDMOS) device includes the steps of first forming a first fin-shaped structure and a second fin-shaped structure on a substrate, forming a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure, forming a first gate structure on the first fin-shaped structure and a second gate structure on the second fin-shaped structure, forming a source region on the first fin-shaped structure, forming a drain region on the second fin-shaped structure, and forming a contact field plate directly on the STI.