公开(公告)号：US20140343880A1

公开(公告)日：2014-11-20

申请号：US13894021

申请日：2013-05-14

Applicant: United Microelectronics Corp.

Inventor： Yi-Ting Wu ,  Cheng-Tung Huang ,  Tsung-Han Lee ,  Yi-Han Ye

IPC: G06F17/11 ,  G01R19/00

CPC classification number: G01R19/0084 ,  G01R31/2621

Abstract: A method for deriving characteristic values of a MOS transistor is described. A set of ηk values is provided. A set of VBi values (i=1 to M, M≧3) is provided. A set of RSDi,j (i=1 to M−1, j=i+1 to M) values each under a pair of VBi and VBj, or a set of Vtq—q,j (q is one of 1 to M, j is 1 to M excluding q) values under VBq is derived for each ηk, with an iteration method. The ηk value making the set of RSDi,j values or Vtq—q,j values closest to each other is determined as an accurate ηk value. The mean value of RSDi,j at the accurate ηk value is calculated as an accurate RSD value.

Abstract translation: 描述用于导出MOS晶体管的特性值的方法。 提供了一组＆eegr k值。 提供一组VBi值（i = 1〜M，M≥3）。 一组RSDi，j（i = 1〜M-1，j = i + 1〜M）的值分别为一对VBi和VBj，或一组Vtq-q，j（q为1〜M ，j为1到M，不包括q）使用迭代方法为每个＆eegr k导出VBq下的值。 使得最接近的RSDi，j值或Vtq-q，j值的集合被确定为精确的k值。 RSDi，j在精确的k值的平均值被计算为准确的RSD值。

公开(公告)号：US09632115B2

公开(公告)日：2017-04-25

申请号：US13894021

申请日：2013-05-14

Applicant: United Microelectronics Corp.

Inventor： Yi-Ting Wu ,  Cheng-Tung Huang ,  Tsung-Han Lee ,  Yi-Han Ye

IPC: G01R19/00 ,  G01R31/26

CPC classification number: G01R19/0084 ,  G01R31/2621

Abstract: A method for deriving characteristic values of a MOS transistor is described. A set of ηk values is provided. A set of VBi values (i=1 to M, M≧3) is provided. A set of RSDi,j (i=1 to M−1, j=i+1 to M) values each under a pair of VBi and VBj, or a set of Vtq_q,j (q is one of 1 to M, j is 1 to M excluding q) values under VBq is derived for each ηk, with an iteration method. The ηk value making the set of RSDi,j values or Vtq_q,j values closest to each other is determined as an accurate ηk value. The mean value of RSDi,j at the accurate ηk value is calculated as an accurate RSD value.

公开(公告)号：US08822297B2

公开(公告)日：2014-09-02

申请号：US13748279

申请日：2013-01-23

Applicant: United Microelectronics Corp.

Inventor： Tsung-Han Lee ,  Cheng-Tung Huang ,  Yi-Han Ye

IPC: H01L21/8249

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

Abstract: Provided is a method of fabricating a MOS device including the following steps. At least one gate structure is formed on a substrate, wherein the gate structure includes a gate conductive layer and a hard mask layer disposed on the gate conductive layer. A first implant process is performed to form source and drain extension regions in the substrate, wherein the gate conductive layer is covered by the hard mask layer. A process is of removing the hard mask layer is performed to expose the surface of the gate conductive layer. A second implant process is performed to form pocket doped regions in the substrate, wherein the gate conductive layer is not covered by the hard mask layer.

Abstract translation: 提供了一种制造MOS器件的方法，包括以下步骤。 在衬底上形成至少一个栅极结构，其中栅极结构包括栅极导电层和设置在栅极导电层上的硬掩模层。 执行第一注入工艺以在衬底中形成源极和漏极延伸区域，其中栅极导电层被硬掩模层覆盖。 执行去除硬掩模层以暴露栅极导电层的表面的工艺。 执行第二注入工艺以在衬底中形成口袋掺杂区域，其中栅极导电层未被硬掩模层覆盖。

公开(公告)号：US20140206170A1

公开(公告)日：2014-07-24

申请号：US13748279

申请日：2013-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Han Lee ,  Cheng-Tung Huang ,  Yi-Han Ye

IPC: H01L29/66

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

Abstract: Provided is a method of fabricating a MOS device including the following steps. At least one gate structure is formed on a substrate, wherein the gate structure includes a gate conductive layer and a hard mask layer disposed on the gate conductive layer. A first implant process is performed to form source and drain extension regions in the substrate, wherein the gate conductive layer is covered by the hard mask layer. A process is of removing the hard mask layer is performed to expose the surface of the gate conductive layer. A second implant process is performed to form pocket doped regions in the substrate, wherein the gate conductive layer is not covered by the hard mask layer.

Abstract translation: 提供了一种制造MOS器件的方法，包括以下步骤。 在衬底上形成至少一个栅极结构，其中栅极结构包括栅极导电层和设置在栅极导电层上的硬掩模层。 执行第一注入工艺以在衬底中形成源极和漏极延伸区域，其中栅极导电层被硬掩模层覆盖。 执行去除硬掩模层以暴露栅极导电层的表面的工艺。 执行第二注入工艺以在衬底中形成口袋掺杂区域，其中栅极导电层未被硬掩模层覆盖。