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    PATTERNED STRUCTURE OF SEMICONDUCTOR DEVICE
    2.
    发明申请
    PATTERNED STRUCTURE OF SEMICONDUCTOR DEVICE 审中-公开
    半导体器件的图案结构

    公开(公告)号：US20150179652A1

    公开(公告)日：2015-06-25

    申请号：US14639994

    申请日：2015-03-05

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Jung Wang ,  Tong-Yu Chen

    IPC: H01L27/11 ,  H01L21/28 ,  H01L21/3213

    CPC classification number: H01L27/11 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/3213 ,  H01L21/823431 ,  H01L21/845

    Abstract: A patterned structure of a semiconductor device includes a substrate, at least a first patterned structure, and at least a second patterned structure. The first patterned structure is a single-layered structure, and the second patterned structure is a multi-layered structure. The width of the second patterned structure is greater than the width of the first patterned structure.

    Abstract translation: 半导体器件的图案化结构包括至少第一图案化结构和至少第二图案化结构的衬底。 第一图案结构是单层结构，第二图案结构是多层结构。 第二图案化结构的宽度大于第一图案化结构的宽度。

    Method of Forming Trench in Semiconductor Substrate
    3.
    发明申请
    Method of Forming Trench in Semiconductor Substrate 有权
    半导体基板中形成沟槽的方法

    公开(公告)号：US20150111385A1

    公开(公告)日：2015-04-23

    申请号：US14582210

    申请日：2014-12-24

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tong-Yu Chen ,  Chih-Jung Wang

    IPC: H01L21/768 ,  H01L21/311

    CPC classification number: H01L21/76807 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144 ,  H01L29/66795

    Abstract: The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.

    Abstract translation: 本发明提供一种在半导体衬底中形成沟槽的方法。 首先，在半导体衬底上形成第一图案化掩模层。 第一图案化掩模层具有第一沟槽。 然后，沿着第一沟槽形成材料层。 然后，在材料层上形成第二图案化掩模层以完全填充第一沟槽。 当保持第二图案化掩模层和半导体衬底之间的材料层的部分以形成第二沟槽时，去除材料层的一部分。 最后，通过使用第一图案化掩模层和第二图案化掩模层作为掩模来执行蚀刻工艺。

    INTERCONNECT STRUCTURE
    4.
    发明申请
    INTERCONNECT STRUCTURE 审中-公开

    公开(公告)号：US20180366364A1

    公开(公告)日：2018-12-20

    申请号：US16109679

    申请日：2018-08-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tong-Yu Chen ,  Chia-Fang Lin

    IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/485

    Abstract: An interconnect layout structure, having a plurality of air gaps, includes a substrate having an insulating material disposed thereon and a conductive line disposed in the insulating material and extending along a first direction. The air gaps are formed in the insulating material and are arranged end-to-end along the first direction and immediately adjacent to a same side of the conductive line. A patterned hard mask is disposed on the conductive line and has a sidewall extending along a second direction that is perpendicular to the first direction and passing between the adjacent air gaps from the top view. A via structure is formed on the conductive line and is electrically connected to the conductive line.

    Semiconductor structure and method of forming a harmonic-effect-suppression structure
    6.
    发明申请
    Semiconductor structure and method of forming a harmonic-effect-suppression structure 有权
    形成谐波抑制结构的半导体结构和方法

    公开(公告)号：US20150221543A1

    公开(公告)日：2015-08-06

    申请号：US14686784

    申请日：2015-04-15

    Applicant: United Microelectronics Corp.

    Inventor： Tong-Yu Chen ,  Kuo-Yuh Yang

    IPC: H01L21/762 ,  H01L21/308 ,  H01L21/265 ,  H01L21/306 ,  H01L21/02

    CPC classification number: H01L21/76224 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02664 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3081 ,  H01L21/76232 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/76898 ,  H01L29/0649

    Abstract: A method of forming a harmonic-effect-suppression structure is disclosed. The method includes: providing a semiconductor substrate having a base semiconductor substrate, a buried dielectric on the base semiconductor substrate, and a surface semiconductor layer on the buried dielectric. Next, a deep trench is formed extending through the surface semiconductor layer and the buried dielectric into the base semiconductor substrate, a silicon layer is formed within a lower portion of the deep trench, the silicon layer allowed to have a top surface height substantially the same as or lower than a top surface height of the base semiconductor substrate, and a dielectric layer is formed within the deep trench and on the silicon layer.

    Abstract translation: 公开了一种形成谐波效应抑制结构的方法。 该方法包括：提供具有基底半导体衬底的半导体衬底，基底半导体衬底上的埋入电介质，以及掩埋电介质上的表面半导体层。 接下来，形成深沟槽，其通过表面半导体层和埋入电介质延伸到基底半导体衬底中，在深沟槽的下部形成硅层，硅层允许具有基本相同的顶表面高度 低于基底半导体衬底的顶表面高度，并且在深沟槽内和硅层上形成电介质层。

    FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF
    7.
    发明申请
    FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF 有权
    场效应晶体管及其制造方法

    公开(公告)号：US20150171194A1

    公开(公告)日：2015-06-18

    申请号：US14636430

    申请日：2015-03-03

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tong-Yu Chen ,  Chih-Jung Wang

    IPC: H01L29/66 ,  H01L21/311 ,  H01L21/28

    CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/42344 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/792

    Abstract: A field effect transistor (FET) and a manufacturing method thereof are provided. The FET includes a substrate, a fin bump, an insulating layer, a charge trapping structure and a gate structure. The fin bump is disposed on the substrate. The insulating layer is disposed on the substrate and located at two sides of the fin bump. The charge trapping structure is disposed on the insulating layer and located at at least one side of the fin bump. A cross-section of the charge trapping structure is L-shaped. The gate structure covers the fin bump and the charge trapping structure.

    Abstract translation: 提供场效应晶体管（FET）及其制造方法。 FET包括衬底，鳍片凸块，绝缘层，电荷俘获结构和栅极结构。 翅片凸块设置在基板上。 绝缘层设置在基板上并且位于散热片凸块的两侧。 电荷捕获结构设置在绝缘层上并位于散热片凸块的至少一侧。 电荷捕获结构的横截面为L形。 栅极结构覆盖鳍片凸起和电荷俘获结构。

    Interconnect structure
    9.
    发明授权
    Interconnect structure 有权

    公开(公告)号：US10658232B2

    公开(公告)日：2020-05-19

    申请号：US16109679

    申请日：2018-08-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tong-Yu Chen ,  Chia-Fang Lin

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485

    Abstract: An interconnect layout structure, having a plurality of air gaps, includes a substrate having an insulating material disposed thereon and a conductive line disposed in the insulating material and extending along a first direction. The air gaps are formed in the insulating material and are arranged end-to-end along the first direction and immediately adjacent to a same side of the conductive line. A patterned hard mask is disposed on the conductive line and has a sidewall extending along a second direction that is perpendicular to the first direction and passing between the adjacent air gaps from the top view. A via structure is formed on the conductive line and is electrically connected to the conductive line.

    INTERCONNECT STRUCTURE, INTERCONNECT LAYOUT STRUCTURE, AND MANUFACTURING METHOD THEREOF
    10.
    发明申请
    INTERCONNECT STRUCTURE, INTERCONNECT LAYOUT STRUCTURE, AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20190214292A1

    公开(公告)日：2019-07-11

    申请号：US16354157

    申请日：2019-03-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tong-Yu Chen ,  Chia-Fang Lin

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: A method for manufacturing an interconnect structure with air gaps includes the following steps. A substrate including a first insulating layer formed thereon is provided. Plural conductive lines are formed in the first insulating layer. A patterned hard mask is formed on the first insulating layer and the conductive lines and exposes portions of the first insulating layer and portions of the conductive lines. The exposed portions of the first insulating layer are then removed to form a plurality of recesses in the first insulating layer. After that, a second insulating layer and a third insulating layer are formed in the recesses to seal the recesses and to form a plurality of air gaps in the recesses. At least two air gaps are respectively formed at two sides of one conductive line of the plurality of conductive lines. A via structure is then formed on the one conductive line.

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