公开(公告)号：US20220069102A1

公开(公告)日：2022-03-03

申请号：US17523946

申请日：2021-11-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jie-Ning Yang ,  Wen-Tsung Chang ,  Po-Wen Su ,  Kuan-Ying Lai ,  Bo-Yu Su ,  Chun-Mao Chiou ,  Yao-Jhan Wang

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/417

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

公开(公告)号：US20190006484A1

公开(公告)日：2019-01-03

申请号：US16043120

申请日：2018-07-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  I-Fan Chang ,  Chun-Ting Chiang ,  Chih-Wei Lin ,  Bo-Yu Su ,  Chi-Ju Lee

IPC: H01L29/51 ,  H01L29/49 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/423 ,  H01L21/28 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/515 ,  H01L21/28088 ,  H01L21/28247 ,  H01L21/32139 ,  H01L21/7682 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate, and the gate structure includes a metal gate electrode. The spacer is disposed on sidewalls of the gate structure, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode. The mask layer is disposed on the gate structure. At least one void is disposed in the mask layer and disposed between the metal gate electrode and the spacer.

公开(公告)号：US10366896B2

公开(公告)日：2019-07-30

申请号：US15688852

申请日：2017-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Fan Chang ,  Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  Jie-Ning Yang ,  Chi-Ju Lee ,  Chun-Ting Chiang ,  Bo-Yu Su ,  Chih-Wei Lin ,  Dien-Yang Lu

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to form a second spacer.

公开(公告)号：US10186594B2

公开(公告)日：2019-01-22

申请号：US15641312

申请日：2017-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ting Chiang ,  Chi-Ju Lee ,  Chih-Wei Lin ,  Bo-Yu Su ,  Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  I-Fan Chang

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/02

Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.

公开(公告)号：US10062764B1

公开(公告)日：2018-08-28

申请号：US15665397

申请日：2017-07-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  I-Fan Chang ,  Chun-Ting Chiang ,  Chih-Wei Lin ,  Bo-Yu Su ,  Chi-Ju Lee

IPC: H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate, and the gate structure includes a metal gate electrode. The spacer is disposed on sidewalls of the gate structure, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode. The mask layer is disposed on the gate structure. At least one void is disposed in the mask layer and disposed between the metal gate electrode and the spacer.

公开(公告)号：US11929418B2

公开(公告)日：2024-03-12

申请号：US17524723

申请日：2021-11-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jie-Ning Yang ,  Wen-Tsung Chang ,  Po-Wen Su ,  Kuan-Ying Lai ,  Bo-Yu Su ,  Chun-Mao Chiou ,  Yao-Jhan Wang

IPC: H01L29/423 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/76838 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/66545

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

公开(公告)号：US11881518B2

公开(公告)日：2024-01-23

申请号：US17523946

申请日：2021-11-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jie-Ning Yang ,  Wen-Tsung Chang ,  Po-Wen Su ,  Kuan-Ying Lai ,  Bo-Yu Su ,  Chun-Mao Chiou ,  Yao-Jhan Wang

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/417

CPC classification number: H01L29/4966 ,  H01L21/76838 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/66545

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

公开(公告)号：US20190043725A1

公开(公告)日：2019-02-07

申请号：US15688852

申请日：2017-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Fan Chang ,  Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  Jie-Ning Yang ,  Chi-Ju Lee ,  Chun-Ting Chiang ,  Bo-Yu Su ,  Chih-Wei Lin ,  Dien-Yang Lu

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L21/28167 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to form a second spacer.

公开(公告)号：US11239082B2

公开(公告)日：2022-02-01

申请号：US16438416

申请日：2019-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Fan Chang ,  Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  Jie-Ning Yang ,  Chi-Ju Lee ,  Chun-Ting Chiang ,  Bo-Yu Su ,  Chih-Wei Lin ,  Dien-Yang Lu

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/51

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to forma second spacer.

公开(公告)号：US20190295849A1

公开(公告)日：2019-09-26

申请号：US16438416

申请日：2019-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Fan Chang ,  Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  Jie-Ning Yang ,  Chi-Ju Lee ,  Chun-Ting Chiang ,  Bo-Yu Su ,  Chih-Wei Lin ,  Dien-Yang Lu

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/423

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to forma second spacer.