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17 条记录 (耗时 0.058 秒)

    Image signal binary circuit with a variable-frequency clock signal generator for driving an image sensor
    1.
    发明授权
    Image signal binary circuit with a variable-frequency clock signal generator for driving an image sensor 失效
    具有用于驱动图像传感器的可变频率时钟信号发生器的图像信号二进制电路

    公开(公告)号：US4839739A

    公开(公告)日：1989-06-13

    申请号：US23262

    申请日：1987-03-09

    申请人： Tsuguji Tachiuchi ,  Satoshi Konuma ,  Nobuo Tsuchiya

    发明人： Tsuguji Tachiuchi ,  Satoshi Konuma ,  Nobuo Tsuchiya

    IPC分类号： H04N1/40 ,  H04N1/403

    CPC分类号： H04N1/403 ,  H04N1/40056

    摘要： A one-dimensional image sensor comprising a solid image pick-up element takes images in sequence, and generates an image signal. Clock pulses from a frequency variable type clock pulse generator having a frequency which varies in correspondence to a control signal are supplied to a one-dimensional image sensor, thereby image signals are outputted in sequence. The image signal is amplified by an amplifier and inputted to a comparator and compared with a reference signal. A frequency variable range of the frequency variable type clock pulse generator is set higher than the cut-off frequency of the amplifier, and the binary level output by the comparator is substantially the same as the image inputted to the one-dimensional image sensor and control is effected by the variable frequency of the clock pulses.

    摘要翻译： 包括实心图像拾取元件的一维图像传感器依次拍摄图像并产生图像信号。 来自具有对应于控制信号变化的频率的频率可变型时钟脉冲发生器的时钟脉冲被提供给一维图像传感器，由此依次输出图像信号。 图像信号被放大器放大并输入到比较器并与参考信号进行比较。 频率可变型时钟脉冲发生器的频率可变范围被设置为高于放大器的截止频率，并且由比较器输出的二进制电平基本上与输入到一维图像传感器的图像和控制 受时钟脉冲的可变频率的影响。

    Data processing apparatus, power supply controller and display unit
    3.
    发明授权
    Data processing apparatus, power supply controller and display unit 失效
    数据处理装置，电源控制器和显示单元

    公开(公告)号：US5511201A

    公开(公告)日：1996-04-23

    申请号：US857629

    申请日：1992-03-25

    申请人： Hideki Kamimaki ,  Kiyokazu Nishioka ,  Tsuguji Tachiuchi ,  Nobuo Tsuchiya ,  Masahiro Jinushi ,  Hitoshi Sadamitsu ,  Hiroshi Ito ,  Takashi Yoshitomi ,  Koichi Isaji ,  Takao Ohba

    发明人： Hideki Kamimaki ,  Kiyokazu Nishioka ,  Tsuguji Tachiuchi ,  Nobuo Tsuchiya ,  Masahiro Jinushi ,  Hitoshi Sadamitsu ,  Hiroshi Ito ,  Takashi Yoshitomi ,  Koichi Isaji ,  Takao Ohba

    IPC分类号： G09G3/34 ,  G06F11/00 ,  G06F11/30

    CPC分类号： G09G3/3406 ,  G09G2320/0606 ,  G09G2320/0626 ,  G09G2330/021 ,  G09G2330/026

    摘要： A data processing apparatus which includes a display unit and a power supply controller for supplying power to the display unit. The display unit has a display screen and a back light controller. The power supply controller comprises a switch, at least one output line for receiving the power from the switch and for supplying therethrough the power to electronic devices, a delay circuit for receiving the power from the switch and when the switch is turned ON to start supply of the power, for outputting the power after passage of a predetermined time from the start of the power supply, and a second output line for supplying the power from the delay circuit to the back light controller therethrough. The display unit has a memory means for storing therein a luminance data on the display screen through the back light controller when the power supply is turned OFF and for determining an output state of the display unit through the back light controller on the basis of the luminance data read out from the memory means when the power supply is turned ON. Further, the data processing apparatus has a means for invalidating output of a display data to be output onto the display screen and a means, after the display data is invalidated, for reducing a frequency of a timing signal or invalidating output of the timing signal for the display unit.

    摘要翻译： 一种数据处理装置，包括显示单元和用于向显示单元供电的电源控制器。 显示单元具有显示屏和背光控制器。 电源控制器包括开关，至少一个输出线，用于从开关接收电力并通过其向电子设备提供电力;延迟电路，用于从开关接收电力;以及当开关接通以开始供电时 的功率，用于在从电源开始经过预定时间之后输出电力;以及第二输出线，用于将来自延迟电路的电力提供给背光控制器。 显示单元具有存储装置，用于当电源关闭时通过背光控制器在其上存储亮度数据，并且通过背光控制器基于亮度来确定显示单元的输出状态 当电源接通时，从存储器读出的数据意味着。 此外，数据处理装置具有使输出到显示屏幕上的显示数据的输出无效的装置和在显示数据无效之后的装置，用于减少定时信号的频率或使定时信号的输出无效， 显示单元。

    Method and apparatus for liquid crystal display with intermediate tone
    4.
    发明授权
    Method and apparatus for liquid crystal display with intermediate tone 失效
    具有中间色调的液晶显示方法和装置

    公开(公告)号：US4808991A

    公开(公告)日：1989-02-28

    申请号：US2198

    申请日：1987-01-12

    申请人： Tsuguji Tachiuchi ,  Hiroyuki Mano ,  Terumi Takashi

    发明人： Tsuguji Tachiuchi ,  Hiroyuki Mano ,  Terumi Takashi

    IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36

    CPC分类号： G09G3/3611 ,  G09G3/2018

    摘要： A liquid crystal display is capable of displaying intermediate, partial or half tones of images, while at the same time preventing the occurrence of flicker and the decay of the liquid crystal panel. The display operation for data to be displayed in an intermediate tone has one or more lines of a repeating frame of display data that are prohibited from being displayed during in each frame. Such inhibited display lines are designated differently on a sequential basis over consecutive frames, and the sequence of designation is varied in successive frames in accord with changing patterns.

    摘要翻译： 液晶显示器能够显示中间，部分或半色调的图像，同时防止发生闪烁和液晶面板的衰减。 要以中间色调显示的数据的显示操作具有在每个帧期间被禁止显示的显示数据的重复帧的一行或多行。 这种被禁止的显示行在连续的帧上以顺序的方式被指定为不同，并且指定序列根据改变的模式在连续的帧中变化。

    Drive circuit for character and graphic display device
    7.
    发明授权
    Drive circuit for character and graphic display device 失效
    字符和图形显示装置的驱动电路

    公开(公告)号：US4388621A

    公开(公告)日：1983-06-14

    申请号：US158263

    申请日：1980-06-10

    申请人： Shigeru Komatsu ,  Shigeru Hirahata ,  Tsuguji Tachiuchi

    发明人： Shigeru Komatsu ,  Shigeru Hirahata ,  Tsuguji Tachiuchi

    IPC分类号： G09G5/24 ,  G06F3/153 ,  G09G1/16 ,  G09G5/00 ,  G09G5/397 ,  G09G5/399 ,  G09G1/00

    CPC分类号： G09G5/001

    摘要： In a .phi..sub.2 cycle steal mode, a clock signal is selected such that a time period during which a RAM is connected to a timing signal generator for display is extended and a time period during which the RAM is connected to a CPU is shortened accordingly, without changing an overall period. This clock signal is used to actuate a switching circuit for the RAM while a clock signal having unmodified duty ratio is applied to the CPU, a ROM and external circuits so that a display data readout period from the RAM is extended without affecting the CPU clock frequency and the operation of other circuits. During this readout period, a plurality of display address signals are applied to the RAM from the timing signal generator and a plurality of data derived from the RAM are sequentially loaded in a register which is then read out at a desired timing to enable the display of a plurality of characters in one CPU clock period.

    摘要翻译： 在phi 2循环盗取模式中，选择时钟信号，使得连接到用于显示的定时信号发生器的RAM的时间段被延长，并且相应地缩短RAM连接到CPU的时间段， 而不改变整个时期。 该时钟信号用于激活用于RAM的开关电路，而具有未修改占空比的时钟信号被施加到CPU，ROM和外部电路，使得来自RAM的显示数据读出周期不会影响CPU时钟频率 和其他电路的操作。 在该读出期间，多个显示地址信号从定时信号发生器施加到RAM，并且从RAM导出的多个数据顺序地加载到寄存器中，然后在期望的定时读出寄存器，以使得能够显示 一个CPU时钟周期内的多个字符。

    Method and apparatus for converting display data form
    8.
    发明授权
    Method and apparatus for converting display data form 失效
    用于转换显示数据格式的方法和装置

    公开(公告)号：US4855728A

    公开(公告)日：1989-08-08

    申请号：US56128

    申请日：1987-06-01

    申请人： Hiroyuki Mano ,  Tsuguji Tachiuchi ,  Kiyoshige Kinugawa ,  Shinji Tanaka

    发明人： Hiroyuki Mano ,  Tsuguji Tachiuchi ,  Kiyoshige Kinugawa ,  Shinji Tanaka

    IPC分类号： G06F3/14 ,  G02F1/133 ,  G06F3/147 ,  G09G3/36 ,  G09G5/00 ,  G09G5/391

    CPC分类号： G09G3/3611 ,  G06F3/1475 ,  G09G2310/0221

    摘要： A data converting system converts CRT display data into display data for another display unit such as a liquid crystal display unit by use of a memory. The system includes a data load controller which selects one segment of data out of two segments of data in the CRT display data successively while changing the segment position to be selected alternately in every two frame scanning periods so that the CRT display data for one complete picture is written into the memory in two frame scanning periods, i.e., a segment is written into the memory once for every two adjacent segments. Display data is read out of the memory in the data form conformable to the other display unit.

    摘要翻译： 数据转换系统通过使用存储器将CRT显示数据转换为诸如液晶显示单元的另一显示单元的显示数据。 该系统包括数据负载控制器，其在CRT显示数据中连续地选择两个数据段中的数据段，同时在每两帧扫描周期中交替地改变要选择的段位置，使得CRT显示数据用于一个完整的图像 在两帧扫描周期中被写入存储器，即，对于每两个相邻的段，将片段写入存储器一次。 以与其他显示单元相符的数据形式从存储器读出显示数据。

    Common memory control system with two bus masters
    9.
    发明授权
    Common memory control system with two bus masters 失效
    普通内存控制系统，带有两个总线主机

    公开(公告)号：US4628482A

    公开(公告)日：1986-12-09

    申请号：US491227

    申请日：1983-05-03

    申请人： Tsuguji Tachiuchi ,  Toyota Honda

    发明人： Tsuguji Tachiuchi ,  Toyota Honda

    IPC分类号： G06F7/00 ,  G06F12/00 ,  G06F13/16 ,  G06F13/28 ,  G06F13/42 ,  G11C11/406

    CPC分类号： G11C11/406 ,  G06F13/1636 ,  G06F13/287 ,  G06F13/42

    摘要： In accordance with the present invention, there is provided a data processing apparatus comprising an MPU which inputs or outputs an address signal and a data signal on the time sharing basis, a latching means for latching said address signal, a memory which must be refreshed, and changeover means for connecting said memory to said MPU during a data signal period and connecting said memory to a refresh counter during remaining periods.

    摘要翻译： 根据本发明，提供了一种数据处理装置，包括：MPU，其基于时间共享输入或输出地址信号和数据信号;锁存装置，用于锁存所述地址信号;必须刷新的存储器; 以及切换装置，用于在数据信号周期期间将所述存储器连接到所述MPU，并且在剩余时段期间将所述存储器连接到刷新计数器。

    Digital data processing device
    10.
    发明授权
    Digital data processing device 失效
    数字数据处理装置

    公开(公告)号：US4368461A

    公开(公告)日：1983-01-11

    申请号：US212232

    申请日：1980-12-02

    申请人： Shigeru Komatsu ,  Kunihiko Nagai ,  Takuo Koyama ,  Tsuguji Tachiuchi ,  Mikiaki Kobayashi ,  Toshiyuki Kurita

    发明人： Shigeru Komatsu ,  Kunihiko Nagai ,  Takuo Koyama ,  Tsuguji Tachiuchi ,  Mikiaki Kobayashi ,  Toshiyuki Kurita

    IPC分类号： G09G5/36 ,  G09G1/16 ,  G09G5/00 ,  G09G5/02 ,  G09G5/34 ,  G09G1/02

    CPC分类号： G09G5/001 ,  G09G5/02

    摘要： A digital data processing device in which a color memory has a temporal data storage register at input/output interface thereof so that the data write-in or data read-out operations executed by a micro-processing unit (MPU) is always performed through the temporal storage register. When data read-out or write-in operation is made to a character memory at a certain address, the same operation is simultaneously carried out for the color memory at the corresponding address. Assuming that MPU reads out a certain display address of a display screen, a corresponding character code is fetched by MPU from the character memory, while the corresponding color code is transferred to the temporal storage register from the color memory. When MPU performs the write-in operation for another address of the display screen, the character code held by MPU until then is written in the character memory at a designated address, while the color data i.e. the contents currently held by the temporal storage register are written in the color memory at the address which corresponds to the designated address of the character memory. In this manner, the color data is simultaneously transferred through the software-based processing for transferring only the character code in appearance, whereby the transfer of the contents to be displayed on the display screen can be carried out with an enhanced efficiency.

    摘要翻译： 一种数字数据处理装置，其中色彩存储器在其输入/输出接口处具有时间数据存储寄存器，使得由微处理单元（MPU）执行的数据写入或数据读出操作总是通过 临时存储寄存器。 当对特定地址的字符存储器进行数据读出或写入操作时，对于相应地址的彩色存储器同时进行相同的操作。 假设MPU读出显示屏幕的某个显示地址，则由MPU从字符存储器取出相应的字符代码，同时将相应的颜色代码从颜色存储器传送到临时存储寄存器。 当MPU对显示画面的另一个地址执行写入操作时，由MPU保持的字符代码以指定地址写入字符存储器，而颜色数据即时间存储寄存器当前保持的内容是 在对应于字符存储器的指定地址的地址处写入彩色存储器。 以这种方式，通过基于软件的处理来同时传送彩色数据，用于仅传送字符代码的外观，从而能够以提高的效率进行显示在显示画面上的内容的传送。