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    Memory device
    2.
    发明授权
    Memory device 失效
    内存设备

    公开(公告)号：US5617360A

    公开(公告)日：1997-04-01

    申请号：US588232

    申请日：1996-01-18

    申请人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

    发明人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

    IPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G11C13/00

    CPC分类号： G06T1/20 ,  G06F7/575 ,  G06T1/60 ,  G09G5/393 ,  G09G2340/10

    摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.

    摘要翻译： 形成在IC芯片上的存储器件包括用于进行数据读取和写入操作的动态随机存取存储器，用于从IC芯片的外部侧接收数据的第一和第二数据端子以及具有连接到IC芯片的第一数据输入端的控制器 用于接收第一数据的数据终端，连接以接收第二数据读取的第二输入，连接到第二数据终端以接收功能模式信号的第三数据输入，以及用于执行从第一数据输入提供的第一数据之间的操作的操作单元 以及从第二输入提供的第二数据。 操作单元包括功能设置单元，其响应于在接收到第一数据之前设置由功能模式信号指示的功能的功能模式信号。 从存储位置的选定部分读出第二数据。 对于第一和第二数据执行与由功能设置单元设置的功能相对应的操作。 在一个存储器周期期间，通过动态随机存取存储器的输入将执行的结果写入存储位置的所选部分。

    Memory circuit with logic functions
    3.
    发明授权
    Memory circuit with logic functions 失效
    具有逻辑功能的存储电路

    公开(公告)号：US5113487A

    公开(公告)日：1992-05-12

    申请号：US314238

    申请日：1989-02-22

    申请人： Toshihiko Ogura ,  Hiroaki Aotsu ,  Koichi Kimura ,  Hiromichi Enomoto ,  Tadashi Kyoda

    发明人： Toshihiko Ogura ,  Hiroaki Aotsu ,  Koichi Kimura ,  Hiromichi Enomoto ,  Tadashi Kyoda

    IPC分类号： G09G5/393

    CPC分类号： G09G5/393 ,  G09G2340/10

    摘要： In a memory circuit having a memory device operative to read, write and hold data and an operation unit implementing computation between a first datum supplied externally and a second datum read out of the memory device, a selector for selecting one of operational function specification data preset externally and a selector for selecting one of bit write control data present externally are given with select control signals, so that a frame buffer memory operative in a read-modify-write mode can be used commonly.

    摘要翻译： 在具有可操作以读取，写入和保持数据的存储器件的存储器电路以及在从外部提供的第一数据和从存储器件读出的第二数据之间实现计算的操作单元中选择一个操作功能指定数据预设 外部选择器和用于选择外部存在的位写入控制数据中的一个的选择器具有选择控制信号，使得可以通常使用以读 - 修改 - 写入模式操作的帧缓冲存储器。

    Graphic system including a plurality of one chip semiconductor integrated circuit devices for displaying pixel data on a graphic display
    5.
    发明授权
    Graphic system including a plurality of one chip semiconductor integrated circuit devices for displaying pixel data on a graphic display 失效
    图形系统包括用于在图形显示器上显示像素数据的多个单芯片半导体集成电路器件

    公开(公告)号：US5838337A

    公开(公告)日：1998-11-17

    申请号：US294406

    申请日：1994-08-23

    申请人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

    发明人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

    IPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G06F15/76

    CPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G09G2340/10

    摘要： A graphic system which includes a display device having a graphic display area which includes a plurality of display portions and a plurality of one-chip semiconductor integrated circuit devices. Each one-chip semiconductor integrated circuit includes memory for storing a plurality of pixel data, each pixel data includes a plurality of bits and color data, and a logic circuit for carrying out logic operation on a unit of one pixel data read out from the memory based on a function signal supplied to the one-chip semiconductor integrated circuit device. The function signal indicates a relation between the unit of one pixel data read out from the memory and pixel data output by the logic circuit. The invention further includes an external device for supplying the function signal to the one-chip semiconductor integrated circuit device. The logic circuits, of the plurality of one-chip semiconductor integrated circuit devices, each carry out the same logic operation in accordance with the function signal. Further the logic circuit of the one-chip semiconductor integrated circuit device outputs pixel data based on the logic operation carried out by the logic circuit so as to display the pixel data from the logic circuit on one of the display portions of the graphic display area of the display device.

    摘要翻译： 一种包括具有包括多个显示部分和多个单芯片半导体集成电路装置的图形显示区域的显示装置的图形系统。 每个单芯片半导体集成电路包括用于存储多个像素数据的存储器，每个像素数据包括多个位和颜色数据，以及用于对从存储器读出的一个像素数据的单元执行逻辑运算的逻辑电路 基于提供给单芯片半导体集成电路器件的功能信号。 功能信号表示从存储器读出的一个像素数据的单位与由逻辑电路输出的像素数据之间的关系。 本发明还包括用于将功能信号提供给单芯片半导体集成电路器件的外部器件。 多个单芯片半导体集成电路装置的逻辑电路各自根据功能信号执行相同的逻辑运算。 此外，单芯片半导体集成电路器件的逻辑电路基于由逻辑电路执行的逻辑运算输出像素数据，以便在逻辑电路的图形显示区域的显示部分之一上显示来自逻辑电路的像素数据 显示设备。

    Address bus control system
    9.
    发明授权
    Address bus control system 失效
    地址总线控制系统

    公开(公告)号：US5301294A

    公开(公告)日：1994-04-05

    申请号：US689556

    申请日：1991-04-23

    申请人： Takahiro Kawai ,  Masatsugu Shinozaki ,  Hitoshi Sadamitsu ,  Tadashi Kyoda ,  Katsuya Takanashi ,  Hironori Uchida

    发明人： Takahiro Kawai ,  Masatsugu Shinozaki ,  Hitoshi Sadamitsu ,  Tadashi Kyoda ,  Katsuya Takanashi ,  Hironori Uchida

    IPC分类号： G06F13/14 ,  G06F12/02 ,  G06F12/06

    CPC分类号： G06F12/0223 ,  G06F12/0661

    摘要： An address bus control system is provided of the type in which a controller including a central processing unit is connected through an address bus and a data bus to hardware modules which control equipment to be controlled. An address space defined by an address bus includes a discrimination space for discriminating the attribute of the hardware module and a function space for allocating and clearing an address space for a function interface of the hardware module. The attribute of a hardware module connected to a connector having a corresponding address is recognized using the discrimination space. The function interface of each hardware module is assigned a space within the function space in accordance with the contents of the discrimination space in concern, or the assigned space is canceled. An address of the function space can be allocated to only a necessary function interface, merely by connecting the hardware module to the connector, allowing to set up hardware modules equal to or larger than the total address space.

    摘要翻译： 提供地址总线控制系统，其中包括中央处理单元的控制器通过地址总线和数据总线连接到控制要控制的设备的硬件模块。 由地址总线定义的地址空间包括用于识别硬件模块的属性的鉴别空间和用于分配和清除硬件模块的功能接口的地址空间的功能空间。 使用识别空间来识别连接到具有相应地址的连接器的硬件模块的属性。 每个硬件模块的功能接口根据关注的鉴别空间的内容在功能空间内分配一个空间，或者分配的空间被取消。 仅通过将硬件模块连接到连接器，可以将功能空间的地址分配给必要的功能接口，允许设置等于或大于总地址空间的硬件模块。

    Integrated memory circuit and function unit with selective storage of logic functions
    10.
    发明授权
    Integrated memory circuit and function unit with selective storage of logic functions 失效
    集成存储器电路和功能单元，具有选择性存储逻辑功能

    公开(公告)号：US5265234A

    公开(公告)日：1993-11-23

    申请号：US13174

    申请日：1993-01-29

    申请人： Toshihiko Ogura ,  Hiroaki Aotsu ,  Koichi Kimura ,  Hiromichi Enomoto ,  Tadashi Kyoda

    发明人： Toshihiko Ogura ,  Hiroaki Aotsu ,  Koichi Kimura ,  Hiromichi Enomoto ,  Tadashi Kyoda

    IPC分类号： G09G5/393 ,  G06F15/62

    CPC分类号： G09G5/393 ,  G09G2340/10

    摘要： In a memory circuit having a memory device operative to read, write and hold data and an operation unit implementing computation between a first datum supplied externally and a second datum read out of the memory device, a selector for selecting one of operational function specification data preset externally and a selector for selecting one of bit write control data present externally are given with select control signals, so that a frame buffer memory operative in read-modify-write mode can be used commonly.

    摘要翻译： 在具有可操作以读取，写入和保持数据的存储器件的存储器电路以及在从外部提供的第一数据和从存储器件读出的第二数据之间实现计算的操作单元中选择一个操作功能指定数据预设 外部选择器和用于选择外部存在的位写控制数据中的一个的选择器给出选择控制信号，使得可以通常使用以读 - 修改 - 写模式操作的帧缓冲存储器。