知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

13 records (took 0.015 seconds)

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20200279841A1

    公开(公告)日：2020-09-03

    申请号：US16549486

    申请日：2019-08-23

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Tomoya SANUKI

    IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L23/528

    Abstract: According to one embodiment, a semiconductor device includes a first substrate and a logic circuit provided on the first substrate. The device further includes a memory cell provided above the logic circuit and a second substrate provided above the memory cell. The device further includes a bonding pad provided above the second substrate and electrically connected to the logic circuit. The device further includes a wiring that is provided above the second substrate, is electrically connected to the memory cell, and includes at least one of a data signal line, a control voltage line, and a power supply line.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210366879A1

    公开(公告)日：2021-11-25

    申请号：US17396810

    申请日：2021-08-09

    Applicant: Toshiba Memory Corporation

    Inventor： Tomoya SANUKI

    IPC: H01L25/065 ,  H01L23/00 ,  G11C5/06 ,  H01L27/11582

    Abstract: In one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. The device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20200286842A1

    公开(公告)日：2020-09-10

    申请号：US16561351

    申请日：2019-09-05

    Applicant: Toshiba Memory Corporation

    Inventor： Tomoya SANUKI

    IPC: H01L23/00 ,  H01L27/11582 ,  G11C5/06 ,  H01L25/065

    Abstract: In one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. The device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads.

    SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD OF SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD OF SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190267097A1

    公开(公告)日：2019-08-29

    申请号：US16114182

    申请日：2018-08-27

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Yusuke HIGASHI ,  Tomoya SANUKI

    IPC: G11C16/26 ,  H01L27/102 ,  H01L27/11582 ,  G11C16/04 ,  G11C11/56

    Abstract: A semiconductor memory device includes an n-type semiconductor region, first to fourth conductive layers above the n-type semiconductor region, a p-type semiconductor region, a semiconductor layer between the n-type semiconductor region and the p-type semiconductor region and extending through the conductive layers, charge storage regions between the conductive layers and the semiconductor layer, a control circuit that executes a first read sequence and a second read sequence following the first read sequence, a comparison circuit that compares the first data read in the first read sequence to the second data read in the second read sequence, and a determination circuit that selects one of the first data and the second data as a true read value. The first and second read sequences each have an off step and an off voltage applied during the first read sequence is different from an off voltage applied during the second read sequence.

Patent Agency Ranking