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公开(公告)号：US4128775A
公开(公告)日：1978-12-05
申请号：US808752
申请日：1977-06-22
IPC分类号： G05F3/20 , H03K19/003 , H03K19/0185 , H03K17/60 , H03K1/02 , H03K1/14 , H03K19/08
CPC分类号： G05F3/20 , H03K19/00384 , H03K19/018507 , H03K19/018521
摘要： The invention described herein is an interface circuit which effectively allows TTL output voltages to fall within the range of CMOS input thresholds. The interface circuit contains bipolar and FET devices connected to generate an input voltage threshold which is equal to two base-emitter voltage drops. The interface circuit also includes a switching circuit portion which comprises one P-channel MOS transistor connected to one N-channel MOS transistor.
摘要翻译： 本文描述的本发明是有效地允许TTL输出电压落入CMOS输入阈值范围内的接口电路。 接口电路包括连接的双极和FET器件，以产生等于两个基极 - 发射极电压降的输入电压阈值。 接口电路还包括开关电路部分，其包括连接到一个N沟道MOS晶体管的一个P沟道MOS晶体管。
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公开(公告)号：US4963802A
公开(公告)日：1990-10-16
申请号：US329261
申请日：1989-03-27
申请人： William H. Gross , James B. Cecil
发明人： William H. Gross , James B. Cecil
IPC分类号： H02P7/00
CPC分类号： H02P7/03
摘要： A logic-controlled circuit superimposes a constant voltage across an actuator or motor load that is driven by a bridge-type amplifier to control the constant velocity operation of such load in response to an applied logic signal that may also disable the bridge-type amplifier.
摘要翻译： 逻辑控制电路跨越由桥式放大器驱动的致动器或电动机负载叠加恒定电压，以响应于也可以禁用桥式放大器的施加的逻辑信号来控制这种负载的恒定速度操作。
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3.发明授权Circuit to reduce dropout voltage in a low dropout voltage regulator using a dynamically controlled sat catcher 失效使用动态控制的sat捕获器来降低低压差稳压器中的压降电压的电路
公开(公告)号：US5410241A
公开(公告)日：1995-04-25
申请号：US036777
申请日：1993-03-25
申请人： James B. Cecil
发明人： James B. Cecil
CPC分类号： G05F3/30
摘要： An integrated circuit voltage regulator employs a PNP pass transistor to produce a low dropout voltage. Saturation in the pass transistor produces excessive substrate current which appears in the form of wasted current which lowers the regulator efficiency. A current conducted by the sat catcher circuit is employed to avoid pass transistor saturation. The sat catcher is controlled dynamically so the dropout voltage is minimized and the voltage regulator maintains good performance at high regulator output currents.
摘要翻译： 集成电路电压调节器采用PNP传输晶体管产生低压降电压。 传输晶体管中的饱和度产生过多的衬底电流，其以浪费电流的形式出现，这降低了调节器的效率。 采用由sat捕获电路传导的电流来避免传输晶体管饱和。 饱和捕获器被动态地控制，使得压差电压最小化，并且电压调节器在高稳压器输出电流下保持良好的性能。
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4.发明授权Statistical enhancement of the accuracy of a ratio-matched network in a circuit chip 失效统计增强电路芯片中比例匹配网络的精度
公开(公告)号：US4224564A
公开(公告)日：1980-09-23
申请号：US911463
申请日：1978-06-01
CPC分类号： H03M1/785
摘要： A statistically enhanced ratio-matched network in a circuit chip is disclosed. The network may be either a resistance network or a capacitance network. In a ratio-matched resistance network, such as an R-2R resistance ladder, a plurality of resistances in a circuit chip have a rational ratio of resistance values to each other. All of the resistances each consists of an integral number of simultaneously fabricated resistors of approximately uniform dimensions, and certain critical resistances each consists of a series-parallel combination of the resistors for statistically enhancing the accuracy of the rational ratio of the critical resistances to each other.
摘要翻译： 公开了一种在电路芯片中统计增强的比匹配网络。 网络可以是电阻网络或电容网络。 在诸如R-2R电阻梯的比匹配电阻网络中，电路芯片中的多个电阻具有彼此的电阻值的合理比率。 所有电阻各自由大致均匀尺寸的整体数量的同时制造的电阻组成，并且某些关键电阻各自由电阻器的串联并联组合组成，用于统计提高临界电阻相互之间的有理比的精度 。
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公开(公告)号：US4878034A
公开(公告)日：1989-10-31
申请号：US329377
申请日：1989-03-27
申请人： William H. Gross , James B. Cecil
发明人： William H. Gross , James B. Cecil
IPC分类号： H03F1/52
CPC分类号： H03F1/52
摘要： An overload protection circuit for a disableable amplifier includes a sensing resistor connected to provide indication of the current supplied to the amplifier and includes logic circuitry for producing a disabling control signal for a selected time interval following detection of the overload condition of the amplifier.
摘要翻译： 用于可禁用放大器的过载保护电路包括连接到提供对放大器提供的电流的指示的感测电阻器，并且包括逻辑电路，用于在检测到放大器的过载状况之后的所选时间间隔内产生禁用控制信号。
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公开(公告)号：US4338590A
公开(公告)日：1982-07-06
申请号：US110135
申请日：1980-01-07
CPC分类号： H03M1/00 , H03M2201/02 , H03M2201/3115 , H03M2201/3131 , H03M2201/3136 , H03M2201/3168 , H03M2201/4135 , H03M2201/4225 , H03M2201/4233 , H03M2201/4262 , H03M2201/6121 , H03M2201/63 , H03M2201/814
摘要： A multi-stage resistive ladder network which uses extra stages to trim out resistance discrepencies. All of the stages are interconnected in a series. Nominally, current is divided in half within each stage. Half of the current is gated onto a bus in response to logic control signals, and the other half of the current is passed onto the next succeeding stage. Due to various processing limitations, the resistors comprising each stage vary slightly from their nominal value, which in turn upsets the current division. To compensate for this additional current dividing stages are serially connected to the last stage of the ladder. Current from these additional stages are selectively coupled onto the bus in response to the logic signals in addition to the current which is normally coupled thereto.
摘要翻译： 一个多级电阻梯形网络，使用额外的级来修剪阻抗差异。 所有的阶段都是相互联系的。 名义上，目前在每个阶段都分成两半。 响应于逻辑控制信号，一半的电流被门控在总线上，而另一半的电流被传递到下一个后续阶段。 由于各种处理限制，包括每个级的电阻器与它们的标称值略有不同，这反过来扰乱了当前的划分。 为了补偿这个额外的电流分级级与梯子的最后阶段串联连接。 来自这些附加级的电流除了通常耦合到其上的电流之外还响应于逻辑信号而选择性地耦合到总线上。
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公开(公告)号：US4267550A
公开(公告)日：1981-05-12
申请号：US115203
申请日：1980-01-25
申请人： James B. Cecil
发明人： James B. Cecil
CPC分类号： H03M1/785
摘要： The disclosed digital to analog conversion circuit is comprised of a plurality of resistors interconnected as an N stage R-2R ladder network, a pair of conductive buses, and a total of N transistorized switches which respectively couple the output legs of the ladder to a selectable one of the buses in response to digital logic signals. Those switches which couple to the legs of the K most significant stages have scaled resistances that differ by powers of two; whereas the remaining switches have resistances which equal the largest scaled resistance. An MOS transistor lies in the serial leg of the Kth stage. This transistor has a resistance of approximately 2/3 the largest scaled resistance of the switches. The unscaled resistances provide for ease of fabrication, while the MOS transistor improves the accuracy with which digital to analog conversions are performed.
摘要翻译： 所公开的数模转换电路包括作为N级R-2R梯形网络互连的多个电阻器，一对导电总线和总共N个晶体管开关，其分别将梯形图的输出端耦合到可选择的 其中一条总线响应数字逻辑信号。 那些耦合到K个最重要阶段的腿的那些开关具有按两个幂的不同的电阻; 而剩余的开关具有等于最大比例电阻的电阻。 MOS晶体管位于第K阶段的连续腿。 该晶体管的电阻大约是开关最大比例电阻的2/3。 不间断电阻提供了易于制造的功能，而MOS晶体管提高了执行数模转换的精度。
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公开(公告)号：US4160244A
公开(公告)日：1979-07-03
申请号：US661124
申请日：1976-02-25
申请人： James E. Solomon , James B. Cecil
发明人： James E. Solomon , James B. Cecil
CPC分类号： H03M1/76
摘要： A digital-to-analog converter having a nonlinear transfer characteristic includes a voltage divider connected in parallel with a reference voltage and a switching array connected to the voltage divider. The switching array is actuated in accordance with the digital word which is being converted to an analog signal. The voltage divider is dimensioned to provide a nonlinear transfer characteristic. The digital-to-analog circuit is also employed for performing a successive approximation analog-to-digital conversion. The voltage divider is an integrated circuit resistor formed of an elongated strip of one polarity diffused in a semiconductor substrate of the opposite polarity, and some of the switches of the array are integrated circuit switches in which a portion of the continuous strip forms one terminal thereof.
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