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公开(公告)号：US4338590A
公开(公告)日：1982-07-06
申请号：US110135
申请日：1980-01-07
CPC分类号： H03M1/00 , H03M2201/02 , H03M2201/3115 , H03M2201/3131 , H03M2201/3136 , H03M2201/3168 , H03M2201/4135 , H03M2201/4225 , H03M2201/4233 , H03M2201/4262 , H03M2201/6121 , H03M2201/63 , H03M2201/814
摘要： A multi-stage resistive ladder network which uses extra stages to trim out resistance discrepencies. All of the stages are interconnected in a series. Nominally, current is divided in half within each stage. Half of the current is gated onto a bus in response to logic control signals, and the other half of the current is passed onto the next succeeding stage. Due to various processing limitations, the resistors comprising each stage vary slightly from their nominal value, which in turn upsets the current division. To compensate for this additional current dividing stages are serially connected to the last stage of the ladder. Current from these additional stages are selectively coupled onto the bus in response to the logic signals in addition to the current which is normally coupled thereto.
摘要翻译： 一个多级电阻梯形网络，使用额外的级来修剪阻抗差异。 所有的阶段都是相互联系的。 名义上，目前在每个阶段都分成两半。 响应于逻辑控制信号，一半的电流被门控在总线上，而另一半的电流被传递到下一个后续阶段。 由于各种处理限制，包括每个级的电阻器与它们的标称值略有不同，这反过来扰乱了当前的划分。 为了补偿这个额外的电流分级级与梯子的最后阶段串联连接。 来自这些附加级的电流除了通常耦合到其上的电流之外还响应于逻辑信号而选择性地耦合到总线上。
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2.发明授权Statistical enhancement of the accuracy of a ratio-matched network in a circuit chip 失效统计增强电路芯片中比例匹配网络的精度
公开(公告)号：US4224564A
公开(公告)日：1980-09-23
申请号：US911463
申请日：1978-06-01
CPC分类号： H03M1/785
摘要： A statistically enhanced ratio-matched network in a circuit chip is disclosed. The network may be either a resistance network or a capacitance network. In a ratio-matched resistance network, such as an R-2R resistance ladder, a plurality of resistances in a circuit chip have a rational ratio of resistance values to each other. All of the resistances each consists of an integral number of simultaneously fabricated resistors of approximately uniform dimensions, and certain critical resistances each consists of a series-parallel combination of the resistors for statistically enhancing the accuracy of the rational ratio of the critical resistances to each other.
摘要翻译： 公开了一种在电路芯片中统计增强的比匹配网络。 网络可以是电阻网络或电容网络。 在诸如R-2R电阻梯的比匹配电阻网络中，电路芯片中的多个电阻具有彼此的电阻值的合理比率。 所有电阻各自由大致均匀尺寸的整体数量的同时制造的电阻组成，并且某些关键电阻各自由电阻器的串联并联组合组成，用于统计提高临界电阻相互之间的有理比的精度 。
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公开(公告)号：US4154530A
公开(公告)日：1979-05-15
申请号：US863279
申请日：1977-12-22
CPC分类号： H01L21/67253
摘要： A laser beam is employed to trim monolithic integrated circuits in wafer form in a step and repeat machine. The step and repeat action is adjusted to bring successive circuits on the wafer into trimming relationship with the laser. The circuit is measured and trimming accomplished to adjust the circuit performance to a precise specification. The step and repeat operation introduces a small error that accumulates as stepping proceeds. A laser beam error detector pattern is incorporated into the integrated circuit wafer and is designed to produce a response when the beam impingement error exceeds a predetermined value. The detector output causes the laser beam to be translated by an increment equal to the error and in the opposite direction. As a result, the laser beam aiming error is controlled by a known pattern rather than by an unknown cumulative error.
摘要翻译： 采用激光束在台阶和重复机器中以晶片形式修整单片集成电路。 调整步进和重复动作以使晶片上的连续电路与激光器进行修整关系。 测量和修整电路以将电路性能调整到精确的规格。 步骤和重复操作引入一个随着步进进行而积累的小错误。 激光束误差检测器图案被并入到集成电路晶片中，并且被设计成当光束冲击误差超过预定值时产生响应。 检测器输出使激光束平移一个等于误差的增量和相反的方向。 结果，激光束瞄准误差由已知的模式而不是未知的累积误差来控制。
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公开(公告)号：US4198622A
公开(公告)日：1980-04-15
申请号：US968329
申请日：1978-12-11
CPC分类号： H03M1/76
摘要： Two digital-to-analog converters are coupled in series across a reference potential source. Each converter includes a resistor ladder and switching tree that permits coupling the output to any single tap on the ladder. A digital word is split into two portions, each one of which operates one switching tree. The converters are weighted in accordance with the word bits applied. The switching tree outputs are combined to produce an analog output related to the reference potential and the digital word.
摘要翻译： 两个数模转换器串联耦合在参考电位源上。 每个转换器包括一个电阻梯和开关树，允许将输出耦合到梯形图上的任何一个分接头。 数字字被分成两部分，每一部分都运行一个切换树。 转换器根据应用的字位进行加权。 开关树输出被组合以产生与参考电位和数字字相关的模拟输出。
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公开(公告)号：US4335371A
公开(公告)日：1982-06-15
申请号：US28464
申请日：1979-04-09
CPC分类号： H03M1/1047
摘要： A single chip integrated circuit analog-to-digital converter uses the successive approximation approach with resistor ladder-switching decoder digital-to-analog coverters coupled to a precision plural input comparator. An on board PROM is provided to store in digital form the information necessary to trim the digital-to-analog converters. The converter is actuated during wafer probing in the manufacturing process and the PROM is programmed with the trim information. Initially, the PROM is bypassed and the digital words needed for accurate trim applied externally. Once the correct trim words are found, the PROM is programmed with the correct words. A 13-bit converter is supplied with ten 7-bit trim words to achieve a fully trimmed product in wafer fabrication.
摘要翻译： 单芯片集成电路模数转换器采用逐次逼近方法，其中电阻梯形开关解码器数模转换器耦合到精密多输入比较器。 提供了PROM，以数字形式存储修剪数模转换器所需的信息。 在制造过程中的晶圆探测期间，转换器被激活，并且PROM用修剪信息编程。 最初，PROM被绕过，并且外部精确修整所需的数字字。 一旦找到正确的修剪词，PROM就用正确的单词编程。 一个13位转换器提供10个7位修剪字，以在晶圆制造中实现完全修整的产品。
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公开(公告)号：US4307338A
公开(公告)日：1981-12-22
申请号：US863280
申请日：1977-12-22
IPC分类号： G01R31/265 , G01R27/02
CPC分类号： G01R31/2656
摘要： A detector for application to integrated circuits useful in determining the alignment of a trimming laser. A metallization pattern is employed along with electrical detection circuitry to determine when the trimming laser becomes misaligned by a predetermined amount. The laser is precision aimed when the integrated circuit wafer is located in a step and repeat machine. As stepping continues the detector provides an indication when the cumulative error exceeds the predetermined value.
摘要翻译： 用于应用于集成电路的检测器，其用于确定修整激光器的对准。 金属化图案与电检测电路一起使用以确定修剪激光器何时变得不对准预定量。 当集成电路晶片位于台阶和重复机器中时，激光是精确瞄准的。 当步进继续时，当累积误差超过预定值时，检测器提供指示。
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公开(公告)号：US4238839A
公开(公告)日：1980-12-09
申请号：US31562
申请日：1979-04-19
IPC分类号： G11C17/00 , G11C17/12 , G11C17/14 , G11C17/16 , H01L21/8246 , H01L23/525 , H01L27/10 , H01L27/112 , G11C17/06
CPC分类号： H01L23/5258 , G11C17/12 , G11C17/16 , H01L2924/0002
摘要： A read only memory is fabricated using metal oxide semiconductor technology and is intended for incorporation into large scale integrated circuits. A plurality of memory transistors is arrayed in a configuration having columns, each of which is associated with an address line, and rows, each of which is associated with a word line. A memory transistor is located at each intersection of an address line and a word line. Each memory transistor represents a bit location and includes a severable conductive link coupled in series and located on top of the field oxide surrounding the memory transistors. Each memory transistor in a particular column has its gate coupled to an address line. Each memory transistor in a particular row completes a series circuit which includes the severable conductive link between a first power supply terminal and a word line. Each word line includes a resistor coupled to the other power supply terminal. When a particular column is addressed, and the associated transistors in the address line turned on, all of the bits in the associated word will be "ones." The memory is programmed as desired after circuit manufacture in the wafer die sort operation by severing selected links with a laser beam. The severed device will program a "zero" into the bit location. The word lines are coupled to a decoder that employs an array of gates having input pairs, one of which displays hysteresis. The memory also includes an external program simulation circuit which permits externally generating a particular digital word to simulate the memory content prior to programming.
摘要翻译： 只读存储器使用金属氧化物半导体技术制造，并且旨在并入大规模集成电路中。 多个存储晶体管以具有与地址线相关联的列和与字线相关联的行的配置排列。 存储晶体管位于地址线和字线的每个交叉点处。 每个存储晶体管表示位位置，并且包括可分离的导电链路，其被串联耦合并且位于围绕存储晶体管的场氧化物的顶部。 特定列中的每个存储晶体管的栅极耦合到地址线。 特定行中的每个存储晶体管完成串联电路，其包括在第一电源端子和字线之间的可分离导电连接。 每个字线包括耦合到另一个电源端子的电阻器。 当寻址特定列并且地址线中的相关联的晶体管导通时，相关联的字中的所有位将为“1”。 通过用激光束切断所选择的链接，在晶片模片分类操作中的电路制造之后，根据需要对存储器进行编程。 切断的设备将对位位置进行“零”编程。 字线耦合到采用具有输入对的门阵列的解码器，其中一个显示滞后。 存储器还包括外部程序模拟电路，其允许外部生成特定数字字以在编程之前模拟存储器内容。
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